1. Multi-objective Topology Synthesis and FPGA Prototyping Framework of Application Specific Network-on-Chip m5141153 Akram Ben Ahmed Xinyu LI, Omar Hammami

2. Outline Introduction Multi-objective NoC Synthesis Flow Evaluation results Summary Research Paper Reading22010/7/12

3. Introduction NoC synthesis problem targets to generate NoC topology for different system design objectives such as system performance and area. Multi-objective NoC synthesis is aimed to optimize the NoC topology and supply Pareto solutions for NoC area and performance. 06/22/2011Research Progress Seminar3

4. Introduction Existing works: – Some focused on single objective synthesis, targeting one parameter without taking care of the remaining ones. – Some were based on multiple objectives synthesis without emphasizing on simulation and execution on FPGA platform. 06/22/2011Research Progress Seminar4

5. Outline Introduction Multi-objective NoC Synthesis Flow Evaluation results Summary Research Paper Reading52010/7/12

6. Multi-objective NoC synthesis workflow: Basic notions The application, represented in the core graph, is divided into Master cores (PEs) and Slave cores (memory units). Routers connecting these cores may have different number of input and output ports.

7. Multi-objective NoC synthesis workflow: Basic notions Multi-objective NoC synthesis aims to decide the convenient number of routers needed besides the number of input and output ports for each router. A maximum number of input output ports is set for each router and should not be exceeded.

8. Multi-objective NoC synthesis workflow Contains the application communication graph

9. Multi-objective NoC synthesis workflow: Core graph Core graph example Slave cores: Memory units Master cores: Processing elements a, b, c, d, e, f denote the communication bandwidth

10. Multi-objective NoC synthesis workflow Generates one initial generation of possible NoC architectures according to parameters

11. Multi-objective NoC synthesis workflow According to the core graph, TLM traffic generator is generated, which represents the master core with the same throughput and traffic distribution and TLM memory model is used, which represents the slave cores.

12. Multi-objective NoC synthesis workflow: Traffic generation According to the core graph Master cores are the responsible for traffic generation and try to communicate with slave cores using OCP IP protocol.

13. Multi-objective NoC synthesis workflow: Traffic generation Traffic generator: execute a c code for traffic generation

14. Multi-objective NoC synthesis workflow: Traffic generation sends the traffic throughput and target address through its Master Fast Simplex Link (MFSL) bus interface.

15. Multi-objective NoC synthesis workflow: Traffic generation Performance onitoring unit: (throughput, average and maximum latency)

16. Multi-objective NoC synthesis workflow: Traffic generation sends back the monitoring information to the processor

17. Multi-objective NoC synthesis workflow: Traffic generation Information can be also sent to Host Pc if needed

18. Multi-objective NoC synthesis workflow The area of each router is obtained from the router library according to their number of input and output ports.

19. Multi-objective NoC synthesis workflow Verifies whether the solution obtained satisfies the constraints

20. Multi-objective NoC synthesis workflow: Fitness verification Performance parameters (Latency, throughput, execution time…) and area fitness are verified. The maximum number of in-out constraint is also verified.

21. Multi-objective NoC synthesis workflow: Fitness verification For each solution violating those constraints, a penalty is added, and then forcing the MOEA to find legal solutions. The MOEA generates new solutions from the new generation and selects the solution that fits the most to the user objectives.

22. Multi-objective NoC synthesis workflow Final and optimal Pareto solutions are selected depending on the user objectives

23. Multi-objective NoC synthesis workflow FPGA prototyping for emulation and validation

24. Outline Introduction Multi-objective NoC Synthesis Flow Evaluation results Summary Research Paper Reading242010/7/12

25. Evaluation results 06/22/2011Research Progress Seminar25 Input Core graph: 8 masters and 4 slaves

26. Evaluation results 06/22/2011Research Progress Seminar26 3 Pareto solutions are obtained with TLM simulation (latency and area utilization)

27. Evaluation results 06/22/2011Research Progress Seminar27 More routers  larger area+ lower latency

28. Evaluation results 06/22/2011Research Progress Seminar28 Less routers  smaller area+ higher latency

29. Evaluation results 06/22/2011Research Progress Seminar29 Comparison between TLM Simulation and FPGA Implementation

30. Evaluation results The latency results of TLM simulation and FPGA emulation are different. The ASIC and FPGA implementation technologies are different. But the relative relationship between the final Pareto solutions rests the same, which means that we can still use TLM simulation to accelerate NoC synthesis, but the final Pareto solution must be validated on RTL. 06/22/2011Research Progress Seminar30

31. Outline Introduction Multi-objective NoC Synthesis Flow Evaluation results Summary Research Paper Reading312010/7/12

32. Summary Multi-objective NoC synthesis based on MOEA technology and prototyping workflow is presented. It offers flexible decisions according to different design objectives and budgets for the designer. 06/22/2011Research Progress Seminar32