1. P08311: FPGA Based multi-purpose driver / data acquisition system Sponsor: Dr. Marcin Lukowiak Team MemberDisciplineRole Andrew FitzgeraldCEProject Manager/FPGA and PC Interface Brian PinkhamEEInput Subsystem – Digital Steven FastowCEFPGA Programming Murtuza QuaizarEEInput Subsystem – Analog Corey VanBlarcomEEOutput Subsystem/Power Management 1

2. Why? Problem ◦ Devices that record digital or analog output provide no way of generating input for a device under test. Solution ◦ Have a reconfigurable device that allows both data sampling and data generation in the digital and analog realms. 2

3. Basically… Logic Analyzer Waveform GeneratorLogic Pattern Generator Output: Input: Oscilloscope 3

4. High Level Customer Needs System Composed of FPGA with embedded processor Embedded processor communicates with attached host computer 2 minute sample time Breakout connections Convenient storage format for recorded data Input Capabilities Digital12 Channels Analog Voltage16 Channels Output Capabilities Digital12 Channels Analog Voltage8 Channels Analog Current8 Channels 4

5. Project breakdown 5

6. Hardware Concept 6

7. GUI Concept 7

8. Technical Risk Assessment POSSIBLE SHOWSTOPPERS Technical Risk Assessment POSSIBLE SHOWSTOPPERS Reaching the analog sample rate desired by our customer ◦ Simulations and prototyping Xilinx IP Cores will expire and become nonfunctional ◦ Requesting an ‘educational donation’ to RIT for the cores ◦ Exploring open cores Java API used by GUI might not communicate with embedded processor ◦ Testing with systems already connected over Ethernet Transfer rate to data storage may not be fast enough ◦ Calculations show feasible ◦ Need more prototyping 8

9. Current Status Current customer needs are met All prototyping parts received with the exception of the USB JTAG programmer Status ◦ Communication has been established between the FPGA and the embedded processor ◦ Simulations of input and output analog hardware have been completed 9

10. Expense Report $326.89 remaining out of $1200.00 initial budget 10

11. Project Schedule 11 MSD I Week 11 – Parts Ordered Design Finalized MSD II Week 1-2 – Parts Arriving Implement at least one full channel of analog from input to output with the FPGA Basic communication between the PC and FPGA implemented PCB for analog daughter board ordered Week 3-6 – Finished PCB Arriving FPGA communication established with GUI on host computer Full system prototype completed Weeks 7-8 Verify design through testing Begin team poster and technical paper Weeks 9-10 Finalize documentation Complete team poster and technical paper

12. Image References Oscilloscope ◦ http://cp.home.agilent.com/upload/cmc_upload/oscillo scope.gif http://cp.home.agilent.com/upload/cmc_upload/oscillo scope.gif Waveform Generator ◦ http://www.em-tek.co.kr/admin/data/33250A.JPG http://www.em-tek.co.kr/admin/data/33250A.JPG Logic Pattern Generator ◦ http://www.n-denkei.com/tektronix_tds2024.jpg http://www.n-denkei.com/tektronix_tds2024.jpg Logic Analyzer ◦ http://www.elexp.com/test/LA-100.jpg http://www.elexp.com/test/LA-100.jpg 12