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CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #15 – Midterm.

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Presentation on theme: "CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #15 – Midterm."— Presentation transcript:

1 CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #15 – Midterm Review

2 Lect-15.2CprE 583 – Reconfigurable ComputingOctober 9, 2007 Project Proposals Group 01 – Real-time Ray-Tracing Scene Manager Architecture Scene data management Ray intersection calculation

3 Lect-15.3CprE 583 – Reconfigurable ComputingOctober 9, 2007 Project Proposals (cont.) Group 02 – FPGA-based Emulation of an 8051 Microprocessor Memory controller Serial interface, ethernet interface

4 Lect-15.4CprE 583 – Reconfigurable ComputingOctober 9, 2007 Project Proposals (cont.) Group 04 – A Prototype for Verifying Application Integrity and Checkpointing Execution Attack detection scheme Hardware-accelerated checkpointing scheme

5 Lect-15.5CprE 583 – Reconfigurable ComputingOctober 9, 2007 Project Proposals (cont.) Group 05 – Implementation of the FP-Growth Algorithm using Reconfigurable Hardware Hardware implementation of systolic tree structure Benchmarking

6 Lect-15.6CprE 583 – Reconfigurable ComputingOctober 9, 2007 Project Proposals (cont.) Group 06 – Real-time Audio Spectrography using FPGA High-speed FFT implementations FPGA interfacing with analog data

7 Lect-15.7CprE 583 – Reconfigurable ComputingOctober 9, 2007 Project Proposals (cont.) Group 07 – True Random Bitstream Generator Interface with true random noise stream Real-time statistical analysis, bias correction

8 Lect-15.8CprE 583 – Reconfigurable ComputingOctober 9, 2007 Project Proposals (cont.) Group 08 – FAP: A Fast Analytical Placer for Large-Scale FPGA Designs Four-phase algorithm integration within VPR Benchmarking with real circuit designs

9 Lect-15.9CprE 583 – Reconfigurable ComputingOctober 9, 2007 Project Proposals (cont.) Group 09 – Implementing the 2-D Wavelet Transform over Reconfigurable Platforms Wavelet function selection Fixed-point quantization analysis

10 Lect-15.10CprE 583 – Reconfigurable ComputingOctober 9, 2007 Project Proposals (cont.) Group 10 – Video Watermarking System for SD MPEG-2 Software implementation for comparison DCT/iDCT computations on FPGA

11 Lect-15.11CprE 583 – Reconfigurable ComputingOctober 9, 2007 Project Proposals (cont.) Group 12 – Web Line-Array Sensor Conveyor-line control Computer vision techniques Line Array Output 100 pixels with 8 bit grey scale each Serialized at 10MHz FPGA Output Presence of tape on product, yes or no Sorting Mechanism Control

12 Lect-15.12CprE 583 – Reconfigurable ComputingOctober 9, 2007 Project Proposals (cont.) Reminders: 11/15 – Project Updates (10 minutes) 12/4-12/6 – Final Presentations (25 minutes) 12/14 – Final Reports

13 Lect-15.13CprE 583 – Reconfigurable ComputingOctober 9, 2007 $ Midterm Review Using the Silicon PE $ MPP PE More Cache PE $ MMX SSE FFTAES CISC Superscalar PE $ Vector PE Reconfigurable Fabric PE Reconfigurable Processor $

14 Lect-15.14CprE 583 – Reconfigurable ComputingOctober 9, 2007 What is Reconfigurable Computing? In its current usage, the term reconfigurable computing refers to some form of hardware programmability Hardware that can be customized using some physical control points Goal: to adapt at the logic level to solve specific problems Some other definitions: (1) systems incorporating some form of hardware programmability – customizing how the hardware is used using a number of physical control points [Compton, 2002] (2) computing via a post-fabrication and spatially programmed connection of processing elements [Wawrzynek, 2004] (3) general-purpose custom hardware [Goldstein, 1998]

15 Lect-15.15CprE 583 – Reconfigurable ComputingOctober 9, 2007 FPGA Technology Various FPGA programming technologies (Anti-fuse, (E)EPROM, Flash, SRAM): SRAM most popular

16 Lect-15.16CprE 583 – Reconfigurable ComputingOctober 9, 2007 Computational Density (Qualitative) FPGAs can complete more work per unit time than a processor or DSP: Less instruction overhead More active computation onto the same silicon area (allows for more parallelism) Can control operations at the bit level (as opposed to word level) Intel Pentium 4 Actel ProASIC

17 Lect-15.17CprE 583 – Reconfigurable ComputingOctober 9, 2007 Generic FPGA Architecture CLB IOB IOBc IOB Input/Output Buffers (IOBs) Configurable Logic Blocks (CLBs) Programmable interconnect mesh Island-style FPGA architecture FPGA = Field-Programmable Gate Array

18 Lect-15.18CprE 583 – Reconfigurable ComputingOctober 9, 2007 LUT-based Logic Element carry logic 4-LUT DFF I1I2I3I4 Cout OUT Each LUT operates on four one-bit inputs Output is one data bit Can perform any Boolean function of four inputs 2 2 4 = 65536 functions (4096 patterns) The basic logic element can be more complex Coarse v. Fine grained Contains some sort of programmable interconnect

19 Lect-15.19CprE 583 – Reconfigurable ComputingOctober 9, 2007 Architectural Issues [AhmRos04A] What values of N, I, and K minimize the following parameters? Area Delay Area-delay product Assumptions All routing wires length 4 Fully populated IMUX Wiring is half pass transistor, half tri-state

20 Lect-15.20CprE 583 – Reconfigurable ComputingOctober 9, 2007 Switch Boxes F s – connections offered per incoming wire Universal switchbox can connect any set of inputs to their target output channels simultaneously Build-able with F s = 3 Xilinx XC4000 switchbox is F s = 3 but not universal Read [ChaWon96A] for more details

21 Lect-15.21CprE 583 – Reconfigurable ComputingOctober 9, 2007 FPGA Memory Resources Individual LUTs can be programmed as 16x1 RAMs and combined to form larger memory structures Block Select+RAM – dedicated blocks of on-chip, true dual port read/write synchronous RAM 4Kb (later 18Kb, 36Kb) of RAM with different aspect ratios Faster, less flexible than distributed RAM using LUTs

22 Lect-15.22CprE 583 – Reconfigurable ComputingOctober 9, 2007 Example FPGA: Xilinx Virtex-II

23 Lect-15.23CprE 583 – Reconfigurable ComputingOctober 9, 2007 FPGA Arithmetic Traditional microprocessors, DSPs, etc. don’t use LUTs Instead use a w-bit Arithmetic and Logic Unit (ALU) Carry connections are hard-wired No switches, no stubs, short wires (1) AND2 OR2 XOR2 (2) ADD SUB CMP 3-LUT (2) ALU AB Out Op (1, 2) 2-LUT AB Out (1) AB Cin Sum Cout Sum Cout / Cin AB

24 Lect-15.24CprE 583 – Reconfigurable ComputingOctober 9, 2007 FPGA Arithmetic (cont.) Hard-wired carry logic support Altera FLEX 8000Xilinx XCV4000

25 Lect-15.25CprE 583 – Reconfigurable ComputingOctober 9, 2007 Arithmetic (cont.) + X0X0 Y0Y0 X1X1 X2X2 X3X3 Z0Z0 Y1Y1 X0X0 + X1X1 + X2X2 + X3X3 Z1Z1 + Y2Y2 ++ + + Y3Y3 ++ + Z2Z2 Carry save multiplication

26 Lect-15.26CprE 583 – Reconfigurable ComputingOctober 9, 2007 LUT-Based Constant Multipliers Constants can be changed in the LUTs to program new multipliers 4-LUT N 0 –N 7 10101011 x NNNNNNNN AAAAAAAAAAAA (N * 1011 (LSN)) + BBBBBBBBBBBB (N * 1010 (MSN)) SSSSSSSSSSSSSSSS Product 4-LUT N 0 –N 7 4-LUT + S 0 –S 15 A 0 –A 11 B 4 –B 15

27 Lect-15.27CprE 583 – Reconfigurable ComputingOctober 9, 2007 Systolic Architectures Goal – general methodology for mapping computations into hardware (spatial computing) structures Composition: Simple compute cells (e.g. add, sub, max, min) Regular interconnect pattern Pipelined communication between cells I/O at boundaries x x +x min xc

28 Lect-15.28CprE 583 – Reconfigurable ComputingOctober 9, 2007 Finite Impulse Response Sequential Memory bandwidth per output – 2k+1 O(k) cycles per output O(1) hardware x + xixi w1w1 x + w2w2 x + w3w3 x + w4w4 yiyi Systolic Memory bandwidth per output – 2 O(1) cycles per output O(k) hardware

29 Lect-15.29CprE 583 – Reconfigurable ComputingOctober 9, 2007 Matrix-Vector Product t = 3 t = 2 t = 1 t = 4 a 31 a 21 a 11 a 41 a 22 a 12 – a 23 a 13 – – a 23 – – – a 14 x1x1 x2x2 x3x3 x4x4 y2y2 y3y3 y4y4 y1y1 t = n+1 t = n+2 t = n+3 t = n xnxn … – – – –

30 Lect-15.30CprE 583 – Reconfigurable ComputingOctober 9, 2007 Splash 1 Architecture F3F3 M3M3 VME Bus Interface VSB Bus Control Interface FIFO IN FIFO OUT M4M4 F4F4 F 11 M 11 M 12 F 12 F0F0 M0M0 M7M7 F7F7 F8F8 M8M8 M 15 F 15 F1F1 M1M1 M6M6 F6F6 F9F9 M9M9 M 14 F 14 F2F2 M2M2 M5M5 F5F5 F 10 M 10 M 13 F 13 F 31 M 31 M 24 F 24 F 23 M 23 M 16 F 16 F 28 M 28 M 27 F 27 F 20 M 20 M 19 F 19 F 29 M 29 M 26 F 26 F 21 M 21 M 18 F 18 F 30 M 30 M 25 F 25 F 22 M 22 M 17 F 17

31 Lect-15.31CprE 583 – Reconfigurable ComputingOctober 9, 2007 Other Multi-FPGA Topologies Crossbar topology: Devices A-D are routing only Gives predictable performance Potential waste of resources for near-neighbor connections ABCD WXYZ

32 Lect-15.32CprE 583 – Reconfigurable ComputingOctober 9, 2007 FPGA-based Router FPX module contains two FPGAs NID – network interface device Performs data queuing RAD – reprogrammable application device Specialized control sequences

33 Lect-15.33CprE 583 – Reconfigurable ComputingOctober 9, 2007 Logic Emulation Emulation takes a sizable amount of resources Compilation time can be large due to FPGA compiles

34 Lect-15.34CprE 583 – Reconfigurable ComputingOctober 9, 2007 ASAP and ALAP Schedules ASAP ALAP

35 Lect-15.35CprE 583 – Reconfigurable ComputingOctober 9, 2007 Recursive Partitioning

36 Lect-15.36CprE 583 – Reconfigurable ComputingOctober 9, 2007 Next Steps VHDL for synthesis Non-conventional reconfigurable architectures HW/SW codesign / high-level compilation Other topics? Second course survey next week Provide general feedback, suggest additional topics

37 Lect-15.37CprE 583 – Reconfigurable ComputingOctober 9, 2007 Midterm Exam Three questions Review Analysis Extension Any paper mentioned in class is fair game Due in 1 week (10/16 – 12:00pm) No class on Thursday! Some restrictions: Work alone Can ask if something is unclear (“what does this mean?” questions, not “how do I do this?” questions) No late submissions – strict WebCT deadline

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