1. Interfacing Data Converters

2. D/A converters Design an O/P port with the address FFh to interface the 1408 D/A converter that is calibrated for 0 to 10V range. Write a program to generate a ramp. calibrate the ciruit for bipolar range  5V. calculate the o/p for input 1000 0000.

4. 1408 is TTL and CMOS compatible logic ckt. 8 inputs Labeling of LSB, MSB of data bus and the 1408 is opposite. (A 1 is MSB fo 1408) 2mA reference current for full scale input. and two power supplies +5 and -15. reference current is determined by R14. Output Io =

5. Fo full scale input (D7 to D0 all =1): The output is 1 LSB less than full scale reference source. The full-scale o/p voltage= 2mA(255/256)x5k =9.961V. So, the ckt is designed for 0 to +10V range.

6. program MVI A, 00H;load AC with first i/p DTOA:OUT FFH;output to DAC MVI B, COUNT;Set B for delay DELAY:DCR B JNZ DELAY INR A;next input JMP DTOA; go back to o/p Delay is necessary – time needed for µP to execute an o/p loop is likely to be less than the settling time of DAC. – slope of the ramp can be varied by changing the delay.

7. D/A in bipolar range A 5 K resistor is connected between reference voltage V ref and the o/p in 4. This will add 1 mA to the o/p in opposite direction. therefore at input full scale the ouput voltage will be (2mA – 1mA)xR f = +5V. I O ’

9. at input 0000 0000 o/p is -5V at input 1000 0000 o/p is

10. A/D converter interface ADC0801 using memory mapped IO and interrupt RST6.5. Write interrupt service routine to read o/p data of the converter, store it in memory and continue to collect data for the specified number of times.

11. ADC0801 is CMOS 8 bit successive approcximation A/D converter. output is 0 to +5V. single supply. two inputs for differential analog inputs requires clock at input CLK IN. frequency range is 100 kHz to 800kHz. has internal clock ckt. whose freq can is calculated = 1/(1.1RC) it has 3 control signal: CS’, WR’ and RD’

13. when WR’ makes transition from high to low, the internal SAR is reset, and the o/p lines go into high impedance. when WR’ makes transition from low to high, the conversion begins. When the conversion is complete, the INTR’ is asserted, and the data is placed on the o/p lines. INTR’ is used to run a subroutine which reads data by asserting RD’ lines low. INTR’ si then reset. Full scale o/p can be restricted to lower range of the inputs by using pin 9 (V ref/2 ).

14. Main program the main program initializes the stack, enable the interrupt (EI), unmask RST6.5 (SIM), and initiate a conversion by writing to port 8000H. The main program should include the initialization of the memory location for storing data ad the counter to count the readings. LXI SP, FFFFH LXI H, 7000H MVI B, COUNT;count bytes are to be read EI MVI A, 08H; load bit pattern to enable 7.5,6.5,5.5 interrupts SIM STA 8000H; initiates the conversion

15. subroutine Service routing for RST 6.5 at location 0034H LDA 8000H; read data MOV M,A;store in memory INX H; points to next memory location DCR B; next count STA 8000H; Start next conversion EI; Enable interrupt again RNZ; return to main if B not zero HLT;End