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An Accurate and Detailed Prefetching Simulation Framework for gem5 Martí Torrents, Raúl Martínez, and Carlos Molina martit@ac.upc.edu Computer Architecture Department UPC – BarcelonaTech
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Outline Introduction Current ruby prefetching solution Our solution Implementation details Case of study Conclusions 2
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Outline Introduction Current ruby prefetching solution Our solution Implementation details Case of study Conclusions 3
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Prefetching Reduce memory latency Bring to a nearest cache data required by CPU Increase the hit ratio Implemented in many commercial processors Erroneous prefetching may produce slowdown Simulation tools should include this capability 4
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Outline Introduction Current ruby prefetching solution Our solution Implementation details Case of study Conclusions 5
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Current ruby prefetching solution 6
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Outline Introduction Current ruby prefetching solution Our solution Implementation details Case of study Conclusions 7
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Our solution 8
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Outline Introduction Current ruby prefetching solution Our solution Implementation details Case of study Conclusions 10
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Implementation details 11 Receives command line options Creates and inits the prefetch engine Manages communication Controller –> Prefetcher And Prefetcher –> Prefetch Queue –> Controller Collects statistics
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Implementation details 12 Accumulates the statistics observed_misses - numMissesObserved Cancelled - numDroppedPrefetches completed - numPrefetchAccepted hit in_cache late – numPartialHits/numHits overflowed page_faults – numPagesCrossed total - numPrefetchRequested unuseful useful queue_merged_requests generated_prefetches_per_t rain - streams numMissedPrefetchBlocks MISS
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Implementation details 13 Collects the requests generated by the engine Checks the page fault error Merges repeated requests
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Implementation details 14 Works as an abstract class Must be inherited by the specific pref Virtual functions must be redeclared – Init: Initialization function – Prefetcher size, distance, aggressiveness, etc. – Observe request: Called on each cache access – Hit/miss, prefetch/no_prefetch, accessed address, etc. – Allocate: Called when data allocated in cache – Same as observe request – Deallocate: Called when evicting from cache – Only evicted address
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Implementation details 15 Notifies the wrapper: – Cache accesses – Cache allocation – Cache evictions Reads from Prefetch Queue Prefetch issued when no Loads/Stores Protocol modification similar to a Load operation Very similar to the current solution
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Implementation details 16 Same as in the L1 but… L2 local hits – Some data that is invalid in L2 but locally allocated L1_GETS does not store in L2 – Protocol modified to store pref requests in L2 Pref queue generates a request for another tile – Request is forwarded to the corresponding tile
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Outline Introduction Current ruby prefetching solution Our solution Implementation details Case of study Conclusions 17
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Case of Study: NoC aware prefetch performance evaluation 18 We tested 3 classical prefetch engines: – Tagged Prefetcher – Reference Prediction Table (RPT) – Global History Buffer (GHB) With the gem5 Simulator using – 16 tiled x86 CPUs – L1 prefetchers – Ruby memory system – MOESI coherency protocol – Garnet network simulator Parsecs 2.1
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Case of Study: Results 19 M. Torrents, R. Martínez, C. Molina. “Network Aware Performance Evaluation of Prefetching Techniques in CMPs”. Simulation Modeling Practice and Theory (SIMPAT), 2014.
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Outline Introduction Current ruby prefetching solution Our solution Implementation details Case of study Conclusions 20
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Conclusions 21 Prefetcher is important and it must be simulated Current solution is ok Our solution goes one step farther – Easy to change/add new prefetch engines – Detailed statistics about prefetching – Garnet can identify prefetching traffic – Useful for statistics or traffic manipulation Current tool can be easily included in new solution Current solution is ok for non prefetch researchers Our tool is better for research related with prefetch
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An Accurate and Detailed Prefetching Simulation Framework for gem5 Martí Torrents, Raúl Martínez, and Carlos Molina martit@ac.upc.edu Computer Architecture Department UPC – BarcelonaTech
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