1. DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory

2. Major Rev 3 Goals Booting to –50°C, or colder Memory Interface Layout PMT Waveform, and Clamping Ringing, Clamping, Baseline Bounce Component Substitutions Deferred: -- Front-End Pulser -- Local Coincidence

3. We’re On Track

4. Rev 3 First Items (4) Boot at -70°C, measured by on-board sensor: from Flash and Configuration Memory Memory test OK at -50°C, at 40 MHz, long term... Good PMT waveforms. Good clamping. Perfect MB – to – Delay board fit Power Under 3W (at CPU @ 80MHz & Memory @ 40MHz) 2 boards: -60°C, 160 MHz CPU, 125 MHz Mem RAP at -60°C

5. Rev 3 Problems PC Fab House Testing Failure Shorts on Top Layer: 2 pcs. 4 shorts Two New Schematic Errors (Mentor/EDIF) Loading/Bill-of-Materials errors Two Footprint errors (QFP-100, Oscillator) Minor, but Unsightly Quirks in Front-End Pulser Waveform - product/brand dependency discovered

6. Rev 4 Changes Component Value Changes -- optimization -- schematic corrections Power Supply Load Balancing (One trace, one resistor) On-Board LED Pulser Power (Several parts) Component Substitutions for Reliability, - A few; mainly inductors… 99% finalized - Availability issues Front End Pulser Corrections Layout Design Rule Optimizations

7. Open Issues Chevette vs. Buick vs. Cadillac quality PCBs ( Class 1, 2, 3) Verification (Qualtest) Split between LBNL and UW e.g. Thermal Cycling: How many? What range? e.g. Vibration Testing: What acceleration? Where? e.g. Humidity: Will UW measure RH at -40°C? at -70°C?? in purged and sealed DOM… (VP H 2 O 0.002mm Hg@-70°C vs. 0.1mm Hg@-40°C vs. 24mm Hg@25°C) >> No problem, says RI…<< Design for EMS, when mature (what measure of maturity?)

8. Late Breaking News Receiving & Testing 12 More Rev 3 Boards - 6 Evenstar boards, 6 Data Circuits boards - Looking good so far; Many loading changes in batch Rev 4 Schematic Updates In Progress - 30% of schematic pages to date - Few additional Components. - Detailed List; Configuration Control

9. Rev 4 schedule Ongoing test stand parallel development (STF) -- To be available 1/23 -- Move to room 50a-6105 11/21Modification Review/approval of Spreadsheet and File III 11/25 Design rules Review  12/15 - 12/19 “line-by-line” Reviews  12/24 - 1/6 Fab  1/7 - 1/20 Assembly  1/23 - 2/19 Acceptance Testing at LBNL (STF based)  2/20 First 20 cards to UW  2/23 - 5/21 integration at UW, verification testing at UW and LBNL

10. The End

11. Changes Spreadsheet