1. Fall 2004EE 3563 Digital Systems Design EE 3563 Encoders  When a device’s output has few bits than the input, it is usually called an “encoder”  It essentially performs the same function, a 1:1 mapping of one number to another  A common encoder is the 2 n -to-n or binary encoder  It performs the opposite function of the binary decoder  For example, may have an 8-to-3 encoder, taking one of eight inputs and mapping that to a binary number  Only one input can be asserted at a time  The next schematic is an active high encoder

2. Fall 2004EE 3563 Digital Systems Design EE 3563 Encoders

3. Fall 2004EE 3563 Digital Systems Design EE 3563 74x148 Priority Encoder  The 74x148 encoder is an active low encoder –Both inputs and outputs are active low  This encoder has enable pins which allow it to be cascaded –Two could be used as a 16-to-4 bit encoder –Four could be used as a 32-to-5 bit encoder, etc.  Allows any number of inputs to be asserted at one time, it will output the code for the highest  See p.379, 380 in the text

4. Fall 2004EE 3563 Digital Systems Design EE 3563 74x148 Priority Encoder

5. Fall 2004EE 3563 Digital Systems Design EE 3563 74x148 Priority Encoder  The priority encoder can be used to allow only one device access to the CPU μPμP Hard Disk Sound Card Keyboard Mouse Printer

6. Fall 2004EE 3563 Digital Systems Design EE 3563 Three State Buffers  Also called a three-state driver  Basically, it has 3 outputs: high, low, high-impedance (high-Z) –High impedance allows it to “disappear” from the circuit  4 physically different types of buffers are shown below  Active-high enable input with a non-inverting output  Active-low enable input with a non-inverting output  The last two symbols are ordinary inverters except that they can be disabled  A 74x541 has eight 3-state buffers in a single package  74x540 has inverting buffers

7. Fall 2004EE 3563 Digital Systems Design EE 3563 Three State Buffers  Three state buffers allow devices to share a common line  Recall our Microcomputer: –Assume that each memory shares the data bus –While one is active, the other 3 must be in the high-impedance state