2. ICC Module 3 Lesson 1 – Computer Architecture 1 / 6 © 2015 Ph. Janson Information, Computing & Communication Computer Architecture Clip 3 – Instruction Encoding School of Computer Science & Communications P. Ienne (charts), Ph. Janson (commentary)

3. ICC Module 3 Lesson 1 – Computer Architecture 2 / 6 © 2015 Ph. Janson Outline ►Clip 0 – IntroductionClip 0 ►Clip 1 – Software technology – Assembler languageClip 1  Algorithms  Registers  Data instructions  Instruction numbering  Control instructions ►Clip 2 – Hardware architecture – Von Neumann’s stored program computer architectureClip 2  Data storage and processing  Control storage and processing ►Clip 3 – Hardware design – Instruction encodingClip 3 ►Harware implementation – Transistor technology  Clip 4 – Computing circuits Clip 4  Clip 5 – Memory circuits Clip 5 ►Hardware performance  Clip 6 – Logic parallelism Clip 6  Clip 7 – Architecture parallelism Clip 7 First clipPrevious clipNext clip

4. ICC Module 3 Lesson 1 – Computer Architecture 3 / 6 © 2015 Ph. Janson Sum of the n first integers Input : r1 Output: r2 1: 01000100001100000000 2: 01011000000100000110 3: 00010010001100110001 4: 00010010000100011111 5: 00011001000000000010 6: 01000100001000110000 From algorithms to computers – Step 3 Hardware Software Sum of the n first integers Input : n Output: m s ← 0 as long as n > 0 s ← s + n n ← n – 1 m ← s Sum of the n first integers Input : r1 Output: r2 1: load r3, 0 2: jump_lte r1, 0, 6 3: add r3, r3, r1 4: add r1, r1, -1 5: jump 2 6: load r2, r3

5. ICC Module 3 Lesson 1 – Computer Architecture 4 / 6 © 2015 Ph. Janson ►One can invent a simple encoding:  A few bits to identify the operation (with 8 bits one could distinguish 256 different operations)  A few bits to identify the registers (with 4 bits one could designate 16 different registers, => Thus with 12 bits one could designate 2 operand registers and 1 destination register)  And so on for the rest … ►Thus 32 or 64 bits are sufficient, just as for encoding a typical number How to encode instructions ? Instructions memory Line Instruction 1: loadr3, 0 2: jump_lte r1, 0, 6 3: add r3, r3, r1 4: addr1, r1, -1 5: jump2 6: loadr2, r3 add registers r3, r3, r1 00010010 0011 0011 0001 000000000000 ? The value 305’336’320 represents the instruction add r3, r3, r1

6. ICC Module 3 Lesson 1 – Computer Architecture 5 / 6 © 2015 Ph. Janson Sum of the n first integers Input : r1 Output: r2 1: load r3, 0 2: jump_lte r1, 0, 6 3: add r3, r3, r1 4: add r1, r1, -1 5: jump 2 6: load r2, r3 Encoding instructions Sum of the n first integers Input : r1 Output: r2 1: 01000100001100000000 2: 01011000000100000110 3: 00010010001100110001 4: 00010010000100011111 5: 00011001000000000010 6: 01000100001000110000 Assembler language Binary machine language

7. ICC Module 3 Lesson 1 – Computer Architecture 6 / 6 © 2015 Ph. Janson Arithm. unit Register bank A complete Von Neumann processor architecture Data memory Instructions memory Instruction pointer + 1 Decoder