1. Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing Fariborz Dadnam Professor Lei He

2. PVT Variations Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing2 Process Variations  Inter-die  Die-to-die variations  Intra-die  Within-die variations  Significant impact on sub-micron technologies Voltage Variations Temperature Variations

3. Silicon Tuning Pre-Silicon Design/layout phase Predictable variations Post-Silicon After fabrication ATE feedback Adaptive circuits Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing3 Our Focus: Clock skew: spatial variation Clock jitter: temporal variation

4. Various PST Approaches Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing4 Dynamically adjust clock skew  Adjustable delay buffers (ADB) and Phase detectors (PD) Adjust the V th of clock buffer transistors  Hot carrier injection (HCI) Path-based learning  Employing statistical timing tools to develop regression simulator … PST: post-silicon tuning

5. Different Techniques’ Objective Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing5 Eliminating the number of PST components  Area, power, cost Optimizing algorithms  Accuracy, speed Organizing PST components  Less components, optimization

6. Quadrantal Ring Tuning (QRT) An Active Post-Silicon Tuning Method for Clock Deskewing over PVT Variations Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing6 From the paper by J. G. Mueller and R. A. Saleh

7. Delay-Locked Loop (DLL) Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing7 A single DLL unit

8. Up/Down Detector (UDD) Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing8 Measures the skew between the reference clock and the leaf (clk L and clk R) Concerns,  Receiving accurate clock signals  Setting up/down thresholds precisely In the locked state, no tuning adjustments will be made UP and DOWN can never both be high simultaneously

9. Thermometer Code Generator and Tunable Buffer (TCG) Converts the control signals (UP/DOWN) from UDD to control word (e.g. 3 -bit) for TB Placed next to TB Two clock-cycle wide One tuning step at a time (TB) Clock buffer/inverter to provide selectable delay Spans whole tuning range Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing9

10. Stable DLL over PVT Variations Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing10 Distribution across entire chip  subject to various intra-die PVT variations Step size ( ss ) Skew threshold ( S th ) ss = tuning_range/(#bits - 1) S th = 1.5 × ss To ensure, DLL locking Loop stability

11. QRT Architecture Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing11 Tuning Zones Clock Buffers Tunable Buffers   Tuning Zones Selection Simpler control of fewer, large tuning zones vs. Higher precision/accuracy of more, small tuning zones UDDs Location Minimize routing and Maximize skew measurement accuracy

12. Single-Level QRT Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing12 Feedback (or tuned) clock of one zone becomes the reference clock of its counter-clockwise neighboring zone!

13. Multi-Level QRT Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing13 Total of sixteen additional UDDs, TCGs, and TBs Tuning range of 50ps for clock level-2 vs. 20ps for clock level-3 The sub-skews within each quadrant will be reduced, and therefore, the overall chip’s clock skew will also be reduced

14. PVT Variation Modeling Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing14 PVT Variations Spatial variations (cone function) z 2 = (x – a) 2 + (y – b) 2 in MATLAB [ z(x, y) cone function] Random variations (Monte Carlo simulation) gauss() function in HSPICE [ Gaussian RV(µ, σ) ] (a, b)

15. Simulation Variables Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing15 Transistors’ – Channel width – Leakage – Capacitors – Resistors Wires’ – Length – Resistance per unit length – Capacitance per unit length

16. Total PVT Variation Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing16 P = P nom + ∆P inter + ∆P spatial (x i, y i ) + ∆P random,i P nom nominal value ∆P inter inter-die variation ∆P spatial intra-die variation, function of location (x, y) ∆P random some amount of random variation

17. Result: Single Level Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing17

18. Result: PVT Variations Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing18 (A)(B) (C) (D) (E)(F)

19. Result: Overall Comparison Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing19 No tuning QRT level-2 only QRT level-2 & 3

20. References Fariborz DadnamMultilevel Ring Tuning for Post-Silicon Active Clock Deskewing20 [1] X. Li, B. Taylor, Y. Chien and L. T. Pileggi, "Adaptive Post-Silicon Tuning for Analog Circuits: Concept, Analysis and Optimization," IEEE, pp. 450-457, 2007. [2] Z. Lak and N. Nicolici, "A New Algorithm for Post-Silicon Clock Measurement and Tuning," IEEE, pp. 53-59, 2011. [3] J. G. Mueller and R. A. Saleh, "Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations," IEEE, vol. 9, no. 6, pp. 973-986, June 2011. [4] S. H. Kulkarni, D. Sylvester and D. Blaauw, "A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering," ICCAD, pp. 39-46, November 2006. [5] J.-L. Tsai, L. Zhang and C. C.-P. Chen, "Statistical Timing Analysis Driven Post-Silicon-Tunable Clock-Tree Synthesis," IEEE, pp. 574-580, 2005. [6] J. G. Mueller and R. Saleh, "A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks," IEEE, pp. 572-577, 2088. [7] S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E. Alon and M. Horowitz, "The Implementation of a 2-Core, Multi-Threaded Itanium Family Processor," IEEE, vol. 41, no. 1, pp. 197-209, January 2006. [8] Y. Pu, X. Zhang, K. Ikeuchi, A. Muramatsu, A. Kawasumi, M. Takamiya, M. Nomura, H. Shinohara and T. Sakurai, "Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits," IEEE, pp. 294-298, 2011. [9] M. Y. Kao, K.-T. Tsai and S.-C. Chang, "A Robust Architecture for Post-Silicon Skew Tuning," IEEE, pp. 774-778, 2011.