Presentation is loading. Please wait.

Presentation is loading. Please wait.

2016-1-29Advanced Processor Group The School of Computer Science A Dynamic Link Allocation Router Wei Song, Doug Edwards Advanced Processor Group The University.

Published byThomasine Alexander Modified over 8 years ago

Similar presentations

Presentation on theme: "2016-1-29Advanced Processor Group The School of Computer Science A Dynamic Link Allocation Router Wei Song, Doug Edwards Advanced Processor Group The University."— Presentation transcript:

1 2016-1-29Advanced Processor Group The School of Computer Science A Dynamic Link Allocation Router Wei Song, Doug Edwards Advanced Processor Group The University of Manchester

2 2016-1-29Advanced Processor Group The School of Computer Science Overview Network-on-a-Reconfigurable-ChipNetwork-on-a-Reconfigurable-Chip The Dynamic Link Allocation Flow control method The Dynamic Link Allocation Router (DyLAR) Conclusion

3 2016-1-29Advanced Processor Group The School of Computer Science The NoRC Platform NoRC: network on a reconfigurable chip Running multimedia applications Connection oriented Stochastic routing algorithm GALS: fully asynchronous routers linked by CHAIN

4 2016-1-29Advanced Processor Group The School of Computer Science Connection Oriented Routing Flit Definitions Request Flit Other Flits

5 2016-1-29Advanced Processor Group The School of Computer Science The High Retry Rate Simulation results of a 6x6 NoC with 12 functions in network. 7% Virtual Channels are required to reduce the retry rate.

6 2016-1-29Advanced Processor Group The School of Computer Science Overview Network-on-a-Reconfigurable-Chip The Dynamic Link Allocation Flow control methodThe Dynamic Link Allocation Flow control method The Dynamic Link Allocation Router (DyLAR) Conclusion

7 2016-1-29Advanced Processor Group The School of Computer Science Major Design Targets Implement some kind of virtual channels Increase the bandwidth of CHAIN links Reduce the area and power of the router

8 2016-1-29Advanced Processor Group The School of Computer Science Increase the bandwidth Asynchronous Links work better with the lower wire count.

9 2016-1-29Advanced Processor Group The School of Computer Science Increase the bandwidth

10 2016-1-29Advanced Processor Group The School of Computer Science Increase the bandwidth Spatial division multiplex (SDM) is a good choice for asynchronous NoCs.

11 2016-1-29Advanced Processor Group The School of Computer Science Problems of SDM SDM has the low bandwidth efficiency. Spare sub-link

12 2016-1-29Advanced Processor Group The School of Computer Science Problems of SDM

13 2016-1-29Advanced Processor Group The School of Computer Science Dynamic Link Allocation Divide the sub-link allocation apart from the path reservation Allocate idle sub-link to active communications that reserved this link All communications fairly compete for the bandwidth

14 2016-1-29Advanced Processor Group The School of Computer Science Overview Network-on-a-Reconfigurable-Chip The Dynamic Link Allocation Flow control method The Dynamic Link Allocation Router (DyLAR)The Dynamic Link Allocation Router (DyLAR) Conclusion

15 2016-1-29Advanced Processor Group The School of Computer Science Dynamic Link Allocation Router (DyLAR)

16 2016-1-29Advanced Processor Group The School of Computer Science Path Reservation Stage

17 2016-1-29Advanced Processor Group The School of Computer Science Data Transmission Stage

18 2016-1-29Advanced Processor Group The School of Computer Science Head-of-line (HOL) Problem

19 2016-1-29Advanced Processor Group The School of Computer Science Backpressure

20 2016-1-29Advanced Processor Group The School of Computer Science Backpressure

21 2016-1-29Advanced Processor Group The School of Computer Science Overview Network-on-a-Reconfigurable-Chip The Dynamic Link Allocation Flow control method The Dynamic Link Allocation Router (DyLAR) ConclusionConclusion

22 2016-1-29Advanced Processor Group The School of Computer Science Conclusion Contribution –A new flow control method –Implement the first asynchronous spatial division router Advantages –Smaller latency under zero load –Larger overall throughput under heavy load –Smaller retry rate (smaller power consumption) Problems –An extra request switch in each router –Extra control logic –Increase the latency to pass a router

23 2016-1-29Advanced Processor Group The School of Computer Science Thank You! Questions?

24 2016-1-29Advanced Processor Group The School of Computer Science Detailed Procedures –Request –Path reserved –Sending data –Release path

25 2016-1-29Advanced Processor Group The School of Computer Science Request Procedure

26 2016-1-29Advanced Processor Group The School of Computer Science Request Procedure

27 2016-1-29Advanced Processor Group The School of Computer Science Request Procedure

28 2016-1-29Advanced Processor Group The School of Computer Science Request Procedure

29 2016-1-29Advanced Processor Group The School of Computer Science Request Procedure

30 2016-1-29Advanced Processor Group The School of Computer Science Request Procedure

31 2016-1-29Advanced Processor Group The School of Computer Science OK Ack

32 2016-1-29Advanced Processor Group The School of Computer Science OK Ack

33 2016-1-29Advanced Processor Group The School of Computer Science OK Ack

34 2016-1-29Advanced Processor Group The School of Computer Science OK Ack

35 2016-1-29Advanced Processor Group The School of Computer Science OK Ack

36 2016-1-29Advanced Processor Group The School of Computer Science OK Ack

37 2016-1-29Advanced Processor Group The School of Computer Science Data Flits

38 2016-1-29Advanced Processor Group The School of Computer Science Data Flits

39 2016-1-29Advanced Processor Group The School of Computer Science Data Flits

40 2016-1-29Advanced Processor Group The School of Computer Science Data Flits

41 2016-1-29Advanced Processor Group The School of Computer Science Data Flits

42 2016-1-29Advanced Processor Group The School of Computer Science Data Flits

43 2016-1-29Advanced Processor Group The School of Computer Science Data Flits

44 2016-1-29Advanced Processor Group The School of Computer Science False Ack

45 2016-1-29Advanced Processor Group The School of Computer Science False Ack

46 2016-1-29Advanced Processor Group The School of Computer Science False Ack

47 2016-1-29Advanced Processor Group The School of Computer Science False Ack

48 2016-1-29Advanced Processor Group The School of Computer Science False Ack

Download ppt "2016-1-29Advanced Processor Group The School of Computer Science A Dynamic Link Allocation Router Wei Song, Doug Edwards Advanced Processor Group The University."

Similar presentations

Bulk-Data Metanet: Virtualization by Example Sergey Gorinsky Applied Research Laboratory Applied Research Laboratory Department of Computer Science and.

Bulk-Data Metanet: Virtualization by Example Sergey Gorinsky Applied Research Laboratory Applied Research Laboratory Department of Computer Science and.
Nick Feamster CS 4251 Computer Networking II Spring 2008

Nick Feamster CS 4251 Computer Networking II Spring 2008
Interconnection Networks: Flow Control and Microarchitecture.

Interconnection Networks: Flow Control and Microarchitecture.
Prof. Natalie Enright Jerger

Prof. Natalie Enright Jerger
QuT: A Low-Power Optical Network-on-chip

QuT: A Low-Power Optical Network-on-chip
A Novel 3D Layer-Multiplexed On-Chip Network

A Novel 3D Layer-Multiplexed On-Chip Network
Fault-Tolerant Network-Interface for Spatial Division Multiplexing Based Network-on-Chip By Anup Das.

Fault-Tolerant Network-Interface for Spatial Division Multiplexing Based Network-on-Chip By Anup Das.
1 Agenda TMA2 Feedback TMA3 T821 Bock 2. 2 Packet Switching.

1 Agenda TMA2 Feedback TMA3 T821 Bock 2. 2 Packet Switching.
Flattened Butterfly Topology for On-Chip Networks John Kim, James Balfour, and William J. Dally Presented by Jun Pang.

Flattened Butterfly Topology for On-Chip Networks John Kim, James Balfour, and William J. Dally Presented by Jun Pang.
Evaluating Bufferless Flow Control for On-Chip Networks George Michelogiannakis, Daniel Sanchez, William J. Dally, Christos Kozyrakis Stanford University.

Evaluating Bufferless Flow Control for On-Chip Networks George Michelogiannakis, Daniel Sanchez, William J. Dally, Christos Kozyrakis Stanford University.
1 Message passing architectures and routing CEG 4131 Computer Architecture III Miodrag Bolic Material for these slides is taken from the book: W. Dally,

1 Message passing architectures and routing CEG 4131 Computer Architecture III Miodrag Bolic Material for these slides is taken from the book: W. Dally,
What is Flow Control ? Flow Control determines how a network resources, such as channel bandwidth, buffer capacity and control state are allocated to packet.

What is Flow Control ? Flow Control determines how a network resources, such as channel bandwidth, buffer capacity and control state are allocated to packet.
Reporter: Bo-Yi Shiu Date: 2011/05/27 Virtual Point-to-Point Connections for NoCs Mehdi Modarressi, Arash Tavakkol, and Hamid Sarbazi- Azad IEEE TRANSACTIONS.

Reporter: Bo-Yi Shiu Date: 2011/05/27 Virtual Point-to-Point Connections for NoCs Mehdi Modarressi, Arash Tavakkol, and Hamid Sarbazi- Azad IEEE TRANSACTIONS.
Allocator Implementations for Network-on-Chip Routers Daniel U. Becker and William J. Dally Concurrent VLSI Architecture Group Stanford University.

Allocator Implementations for Network-on-Chip Routers Daniel U. Becker and William J. Dally Concurrent VLSI Architecture Group Stanford University.
Module R R RRR R RRRRR RR R R R R Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip Zvika Guz, Isask ’ har Walter, Evgeny Bolotin, Israel.

Module R R RRR R RRRRR RR R R R R Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip Zvika Guz, Isask ’ har Walter, Evgeny Bolotin, Israel.
High Performance Router Architectures for Network- based Computing By Dr. Timothy Mark Pinkston University of South California Computer Engineering Division.

High Performance Router Architectures for Network- based Computing By Dr. Timothy Mark Pinkston University of South California Computer Engineering Division.
Packet-Switched vs. Time-Multiplexed FPGA Overlay Networks Kapre et. al RC Reading Group – 3/29/2006 Presenter: Ilya Tabakh.

Packet-Switched vs. Time-Multiplexed FPGA Overlay Networks Kapre et. al RC Reading Group – 3/29/2006 Presenter: Ilya Tabakh.
1 Lecture 23: Interconnection Networks Paper: Express Virtual Channels: Towards the Ideal Interconnection Fabric, ISCA’07, Princeton.

1 Lecture 23: Interconnection Networks Paper: Express Virtual Channels: Towards the Ideal Interconnection Fabric, ISCA’07, Princeton.
Lei Wang, Yuho Jin, Hyungjun Kim and Eun Jung Kim

Lei Wang, Yuho Jin, Hyungjun Kim and Eun Jung Kim
1 Link Division Multiplexing (LDM) for NoC Links IEEE 2006 LDM Link Division Multiplexing Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar Technion –

1 Link Division Multiplexing (LDM) for NoC Links IEEE 2006 LDM Link Division Multiplexing Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar Technion –

Similar presentations

Ads by Google