1. CLICpix2 Design Status Pierpaolo Valerio and Edinei Santin
CLICdp Vertex Meeting - August 12th 2015

2. Digital Design Part
Pierpaolo Valerio

3. Suggestions from the DR
Packet format change
SPI interface
DAC reset/read
Enable signal for Power Pulsing
Automatic Test Pulse generator
PRBS generator
ToA Validation with full column simulation

4. Ethernet packet encapsulation
As suggested, now the datastream is properly divided into packets, each containing data from a double column
The idle pattern for synchronization complies with the Ethernet specifications
These modifications should make the data format much more easily readable

5. More standard SPI interface
The SPI interface now always works with a 8bit address + 8bit data format
Every time data is written in a configuration register, old data is shifted out for debug purposes CS
DATA_IN
address
data
DATA_OUT
data

6. New programming algorithm
Using the SPI interface, matrix programming is now done using a standard command, 8 bits at a time
This makes implementing the DAQ firmware easier, but it comes at the cost of additional overhead when performing the programming routine

7. PRBS for link testing
There is now a command to have the chip send a sequence of pseudo-random data to test the error rate of the link between the chip and the DAQ
The same command stops the data stream
The sequence is periodic with a very long period (65k words)

8. Automatic Test-Pulse generator
The chip can now be programmed to generate a sequence of test pulses automatically
Both the number of pulses and the delay between them can be programmed independently; enough test pulses can be produced to saturate the 13-bit event counter
It is still possible to use an external trigger if needed

9. Other features
DACs are now reset at the nominal values when the global reset signal is asserted
It is possible to disable the power pulsing with a configuration option
The power pulsing logic will still be used, but the biasing lines will not be switched

10. Full column ToA simulation
A full column was simulated with a fully extracted digital model and a simplified analog model to check for the validity of the ToA measurements
The analog pixel has “realistic” noise and mismatch models
Sending a pulse to all pixels at the same time, the expected behavior is to have two different ToA results (due to the unknown phase of the input pulse related to the clock)

11. Full column ToA simulation
1000 test pulses were injected with random arrival and shutter times in the simulation
Without noise and mismatch the ToA had no errors (only two values are recorded)
With noise and mismatch, we have an error rate of ~0.013%

12. Things left to do Check the feasibility of the fastor signal
Code cleanup
Some minor suggestions made during the code review need to be implemented
Simulation of the interface with the DAQ
Placing DDR buffer
Synthesis of the periphery
Simulation of extracted periphery + pixel matrix

13. Analog Design Part
Edinei Santin

14. DR points covered here
Further verification of the frontend in terms of PSRR and stability/noise wrt to leakage current and input capacitance
Verification of the output swing of the comparator
New topology for the calibration DAC
Crosstalk between pixels

15. PSRR definition
For both Vdd and Vss, the PSRR is defined as the inverse of the transfer function from the specific rail to the output. Hence, the higher the PSRR, the better the circuit is in rejecting noise from the supply/ground lines.

16. PSRRdd & PSRRss (xRC)
For most of the spectrum, PSRRss is worst than PSRRdd
PSRR degradation is mainly caused by the devices Min and Mload (see previous slide)
Example: A ripple of 1 mV at ~3 MHz on the Vss line will cause ~17 mV at the CSA output  pay particular attention on the power supplies design

17. Ileak & Cin effects on FE stability (xRC)
Holes collection mode; Qin = 5 ke-
Stability verified in time domain to avoid ambiguous loop gain frequency response (i.e. non-monotonic phase)
Overshoot varies < 1.5% for a wide range of Ileak/Cin values  small impact on FE stability
Settling time is almost independent of Ileak

18. Ileak & Cin effects on FE noise (xRC)
Input-referred noise increases considerably with Cin, but it’s almost independent of Ileak
The noisier devices are Min (27.5%), M1a (15.6%), and M2 (13.5%), i.e., the ones connected to the input node of the CSA
Noise spec (70e-) is fulfilled for Cin < ~30 fF

19. Comparator output swing
Comparator core and inverter at different power domains: Vdda = 1.2V and Vddd = 1.0V
Question: Is the output swing of the comparator enough to drive the CMOS inverter following it if Vddd is increased to 1.2V (e.g. to use a single power supply)?

20. Comparator swing vs Qin (xRC)
comp diff in
comp out
inv out
Well-defined output states for Qin > ~600 e-  the output swing of the comparator is large enough to properly drive the CMOS inverter powered at 1.2V
Maximum output swing of the comparator is ~1V

21. Rafa’s cal. DAC topology
Original topology
Rafa’s topology
Rafa’s topology covers 15Ilsb differentially while the original one covers 28Ilsb. Hence, the Ilsb value must be doubled to span the same range.
Power dissipation keeps the same because current sources are more or less halved
Area of the current sources is roughly reduced by a factor of two

22. Cal. DAC correction limits (xRC)
Original topology
Rafa’s topology
6σ FE spread is ~50mV  Ilsb,nom ~25nA (original) and ~50nA (Rafa)
INL is better than 0.5 LSB for Ilsb as large as twice the required value for both topologies

23. Cal. DAC mismatch (xRC)
Original topology
Rafa’s topology
100-case MC analyses show the INLs of the cal. DACs are always within 0.5 LSB
The worst-case INL is 0.32 LSB (original) and 0.30 LSB (Rafa’s topology). That is, both topologies have similar performance in terms of matching with the same transistors sizing

24. New FE layout
Previous layout
New layout

25. Crosstalk between pixels
Two superpixels have been extracted to accurately represent inter-pixel neighborhoods
To achieve a manageable extracted netlist, only C+CC parasitics have been extracted
Pixel 1 excited and crosstalk observed in pixels 2 to 5
Input clock of the digital circuitry running at 100 MHz
Also taken into account: analog/digital Vdd/Vss modeling (next slide), parasitic diodes, and multiple ground regions

26. Power/ground lines modeling
Simple model contemplates bond wire inductance (Lb), series resistance (Rs), and on-chip bypass capacitance (Cbyp)
Typical values (coarse approximation) for Lb, Rs, and Cbyp are indicated

27. Crosstalk at the input of the comparators (xRC)1 2
~41mV 4 3 5
Maximum error due to crosstalk is ~0.5 mV (15e-) which is ~5x lower than the noise spec (70e-)

28. To-do list Improve the design of the periphery DAC buffers
Add cascode current mirrors in the periphery DACs to enhance their linearity
Increase the resolution of the periphery ‘test pulse’ DAC and do a full simulation of the test pulse circuitry
Reduce the Ikrum tuning range by changing the current mirror ratio in the corresponding periphery DAC
Integrate the bandgap block
Final chip assembly and verification

29. Thank you!

30. Backup slides

31. Parasitic diodes extraction
Example of extracted diodes
Rules file has two “switches” to enable the extraction of parasitic diodes (they aren’t extracted by default!)

32. Multiple ground regions (1/3)
The parasitics extraction software used (Calibre) has a way to define multiple ground regions (VSSA and VSSD in this example). Hence, the extracted intrinsic capacitances are referenced to the appropriate ground.

33. Multiple ground regions (2/3)

34. Multiple ground regions (3/3)
Example of extracted parasitic capacitances without and with multiple ground regions definition