1. M. Raymond, Imperial College London IEEE NSS, Rome 20041 The MGPA ECAL readout chip for CMS Mark Raymond, Geoff Hall, Imperial College London, UK. Jamie Crooks, Marcus French, Rutherford Appleton Laboratory, UK. IEEE Nuclear Science Symposium, Rome 2004 Multi–Gain Pre-Amplifier - 0.25  m CMOS chip for CMS ECAL OUTLINE Introduction & background Design Measured Performance Conclusions

2. M. Raymond, Imperial College London IEEE NSS, Rome 20042 CMS Electromagnetic Calorimeter ECAL X-section PbWO 4 crystals ~ 75,000 Lead Tungstate scintillating crystals 60,000 barrel, 15,000 end-cap Hostile radiation environment ionizingneutrons barrel10 kGy2.10 13 n/cm 2 end-cap25 kGy5.10 13 n/cm 2 2.2 x 2.2 cm 2 23 cm ECAL barrelend-cap Compact Muon Solenoid PbWO 4 crystals

3. M. Raymond, Imperial College London IEEE NSS, Rome 20043 Crystal Readout 2 different types Barrel - Avalanche Photodiode (APD) good for high transverse magnetic field not so radiation hard 2/crystal -> ~ 200 pF detector capacitance 60 pC full-scale signal End-cap - Vacuum Photo-Triode (VPT) better radiation hardness OK for lower transverse magnetic field in end-cap v. low capacitance but cabling adds ~ 50 pF 16 pC full-scale signal challenge for front end readout chip 2 different signal sizes and input capacitances prefer to have just one chip for both APDs VPT

4. M. Raymond, Imperial College London IEEE NSS, Rome 20044 Front End Architecture CMS ECAL dynamic range requirement ~ 16 bits to cover range from noise to full-scale signal General approach use multiple gain ranges -> high resolution with only 12 bit ADC only transmit value for highest gain channel-in-range => have to take decision on front end every 25 ns (LHC bunch spacing) Earlier version of CMS ECAL architecture range decision taken in preamplifier (complex chip), followed by single channel commercial ADC New architecture proposed following major ECAL electronics review, early 2002 3 parallel gain channels (MGPA), multi-channel ADC, range decision taken by logic in ADC chip use 0.25  m CMOS (used extensively in CMS) because of: short production turnaround, high yield, cost savings well known radiation hardness Short timescale for development design begun mid 2002, first submission early 2003, fortunately worked well final version (only minor design revisions) available Spring 2004 1 6 12 MGPA 12 bits 2 bits range LOGIC Multi-channel ADC 12 bit ADCs APD/VPT

5. M. Raymond, Imperial College London IEEE NSS, Rome 20045 MGPA Target Specifications ParameterBarrel (APD)End-Cap (VPT) fullscale signal60 pC16 pC noise level (ENC)10000e (1.6 fC)3500e (0.56 fC) input capacitance~ 200 pF (APD)~ 50 pF (cable) output signals (to match ADC) differential 1.8 V,  0.45 V around Vcm = Vdd/2 = 1.25 V gain ranges 1, 6, 12  10 % pulse shaping40 ns CR-RC nonlinearity (each range) <  0.1 % fullscale pulse shape matching (Vpk-25)/Vpk <  1 % within and across gain ranges Barrel/Endcap read out using APD/VPT different capacitance and photoelectric conversion factors 3 gain ranges (1:6:12) sufficient to deliver required physics performance 40 ns pulse shaping trade-off between pile-up and noise (25 ns LHC bunch spacing) linearity and pulse shape matching specs demanding Vpk-25Vpk

6. M. Raymond, Imperial College London IEEE NSS, Rome 20046 MGPA Architecture RFRF R G1 diff. O/P stages CFCF V CM CICI RIRI gain stages RIRI DAC I 2 C and offset generator ext. trig. input stage C F chosen for max. poss. gain value depends on barrel/end-cap R F chosen for 40 ns decay avoids pile-up C F R F external components => 1 chip suits barrel & end-cap differential O/P stages current in, diff. current out external termination 2R I C I = 40 nsec. => low pass filtering on all noise sources within chip 3 gain stages 1:6:12 set by resistors (on-chip), feeding common-gate stages I 2 C interface to program: output pedestal levels DAC for test pulse (ext. trig.) C CAL R G2 R G3 I/P V CM CICI RIRI RIRI CICI RIRI RIRI RFCFRFCF i i i input stage charge amp. V CM

7. M. Raymond, Imperial College London IEEE NSS, Rome 20047 Noise Sources input stage high C f (low gain) to cope with large full-scale signals => corresponding low R f for 40 ns time const. => R f noise dominates over input FET barrel ENC (C IN =200pF) end-cap ENC (C IN = 50 pF) R f noise4900 e2700 e I/P FET1800 e660 e total5220 e2780 e gain stage contribution can’t avoid for low gain range (R G big) but this range only used for larger signals where electronic noise contribution to overall energy resolution negligible input stage RGRG common-gate gain stage i CG i RG C IN v FET source follower diff. output stage v Rf RfRf CfCf barrel: Cf//Rf=33p//1k2 end-cap: Cf//Rf=8p2//4k7

8. M. Raymond, Imperial College London IEEE NSS, Rome 20048 Chip Layout I2C 1 st stage high gain stage diff. O/P stage offset gen. layout issues gain channels segregated as much as poss. with separate power pads -> try to avoid inter-channel coupling lots of multiple power pads die size ~ 4mm x 4mm packaged in 100 pin TQFP (14mm x 14mm) mid gain stage low gain stage diff. O/P stage

9. M. Raymond, Imperial College London IEEE NSS, Rome 20049 Measured Output Pulse Shapes Volts time [nsec] low gain range mid gain range high gain range differential O/P signals from all 3 gain ranges 0 – 60 pC, 40 steps (logarithmic spacing) no signs of distortion in lower gain ranges when higher ranges saturate => effective gain channel separation in layout gain ratios 1 : 5.6 : 11.0 (c.f. 1 : 6 : 12) linear range

10. M. Raymond, Imperial College London IEEE NSS, Rome 200410 Nonlinearity MGPA Version 1 MGPA Version 2 Nonlinearity given by: pk.pulse height – fit (to pk.ht.) fullscale signal 10 chips measured for each MGPA version v. similar results V1 cf. V2 nonlinearity within (or close to) ± 0.1% specification Nonlinearity [% fullscale] charge injected [pC] high gain range mid low mid low high

11. M. Raymond, Imperial College London IEEE NSS, Rome 200411 Pulse Shape Matching high mid low normalise all 33 pulse shapes to max pulse ht. and superimpose Vpk Vpk-25 (Average PSMF = average over all pulse shapes for all 3 gain ranges) PSMF = Vpk-25 Vpk Pulse Shape Matching = (PSMF – Average PSMF) Average PSMF ± 1% spec. Output pulses spanning full-scale range for all 3 gains (11 / range)

12. M. Raymond, Imperial College London IEEE NSS, Rome 200412 Noise ENC [rms electrons] added capacitance [pF] high gain chan.mid gain chan. high gain chan. weak dependence on input capacitance as expected within spec. for high and mid-gain ranges: barrel < 10000 e, end-cap < 3500 e low gain range: barrel: 27300 e ± 12% end-cap: 8200 e ± 11% completely dominated by gain stage noise but signals large so < 0.2% contribution to overall energy resolution BARRELEND-CAP 7240+5.8/pF 3040+4.5/pF 3270+4.5/pF 7870+4.9/pF

13. M. Raymond, Imperial College London IEEE NSS, Rome 200413 Radiation Tests 10 keV X-rays (spectrum peak), dosimetry accurate to ~ 10%, doserate ~ 1 Mrad/hour, no anneal ~ 3% reduction in gain after 5 Mrads (50 kGy, 2 x end-cap worst case) no measurable effect on other performance parameters (noise, linearity, PSM ….) lowmidhigh pre-rad 5 Mrads

14. M. Raymond, Imperial College London IEEE NSS, Rome 200414 On-chip Test Pulse ext. 10pF MGPA I/P Volts nsec. simple DAC allows programmable (I 2 C) amplitude charge injection -> range of signal sizes for each gain range external trigger required allows functional verification during chip screening and in-system I2C external edge trigger

15. M. Raymond, Imperial College London IEEE NSS, Rome 200415 Conclusions MGPA development successful – architecture suits both barrel and end-cap detector regions Analogue performance good gain linearity pulse shape matching noise rad-hard as expected power consumption 600 mW Current status 1 st barrel supermodule contructed at CERN (barrel segment, 1700 channels) performance as expected (excellent noise uniformity) wafer mass production complete – large nos. packaged chips already available within (or v. close to) spec. 5 channel VFE card

16. M. Raymond, Imperial College London IEEE NSS, Rome 200416 Test Bench pulse gen. prog. attenuator 14-bit VME ADC MGPA test board automated, controlled by PC running LabVIEW 14-bit VME ADC need high precision to measure performance to 12-bit level MGPA socketed on test board allows chip to chip comparison without change of external components prog. delay

17. M. Raymond, Imperial College London IEEE NSS, Rome 200417 Transistor Level Schematic

18. M. Raymond, Imperial College London IEEE NSS, Rome 200418 Barrel Energy Resolution x 12x 6x1

19. M. Raymond, Imperial College London IEEE NSS, Rome 200419 Pulse Shape Measurements Volts time [nsec] low gain rangemid gain rangehigh gain range O/P signals probed individually 0 – 60 pC, 40 steps saturation in mid and high gain ranges no clamping outside linear range

20. M. Raymond, Imperial College London IEEE NSS, Rome 200420 I 2 C Pedestal Adjust Volts nsec. I2C=0 I2C=50 I2C=100 VCM ADC I/P range High gain range, ~ fullscale signal. I2C pedestal adjust sets offset current to diff O/P stage (one for each gain range) I2C ~ 50 about right in this case

21. M. Raymond, Imperial College London IEEE NSS, Rome 200421 Linearity and Pulse Shape Matching important for simple reconstruction of “true” pulse shape from samples coming from different gain ranges target specifications non-linearity <  0.1 % fullscale (each gain range) pulse shape matching factor: Vpk-25/Vpk <  1 % within and across all 3 gain ranges low gain range high gain range linearize 12-bit range 25 ns samples Vpk-25 Vpk