1. Chapter 6 Multi-channel Buffered Serial Port (McBSP)

2. Chapter 6, Slide 2Objectives  Definition of Terms:  Bit, word or channel, frame and phase.  Understand basic serial port operation.  Understand clock generation.  Pin polarity.  Serial port interrupts.  Describe multi-channel operation.  Programming the serial port.

3. Chapter 6, Slide 3 Basic Definitions: Bits, Words ? SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port CLK b7b6b5b4b3b2b1b0 Word FS a1a0 Bit Data  “Word” or “channel” contains #bits specified by WDLEN1 (8, 12, 16, 20, 24, 32). RWDLEN157XWDLEN1 57  “Bit” - one data bit per SP clock period. Data Data

4. Chapter 6, Slide 4 Basic Definitions: Frame? SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port  “Frame” - contains one or multiple words  FRLEN1 specifies #words per frame (1-128) RWDLEN1 57 XWDLEN1 57 RFRLEN1814 XFRLEN1 8 14 w0w1w2w3w4w5w6w7 Frame Word w6w7 Data FS

5. Chapter 6, Slide 5 Basic Definitions - Phase FS Phase 1 Phase 2 AB321 Data Frame SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port RFRLEN1RWDLEN1 58 14 7 XFRLEN1XWDLEN1 58 14 RFRLEN2RWDLEN223242130XFRLEN2XWDLEN2 23242130 PHASE31PHASE 31 7 Phase 2 Phase 1  Note: dual-phase used in Audio Codec97 (AC97) Std  Each PHASE can contain different #bits ( WDLEN1/2 ) and #words ( FRLEN1/2 ).  Each FRAME can contain only 1 or 2 PHASES ( PHASE ).

6. Chapter 6, Slide 6 Basic Definitions - Phase FS AB321 Phase 1 Phase 2 Data Frame SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port RFRLEN2PHASERWDLEN2RFRLEN1RWDLEN1 58 232414213031 7 XFRLEN2PHASEXWDLEN2XFRLEN1XWDLEN1 58 232414213031 7  From above example some of the bit fields of RCR and XCR can be initialised as shown below. 1100010001010010 00100010 000000 816  Each PHASE can contain different #bits ( WDLEN1/2 ) and #words ( FRLEN1/2 ).  Each FRAME can contain 1 or 2 PHASES ( PHASE ). Phase 2 Phase 1

7. Chapter 6, Slide 7ExerciseFS A1 Phase 1 Phase 2 Data Frame  Fill in the control values for the example above. RFRLEN2PHASERWDLEN2RFRLEN1RWDLEN1 58 232414213031 7 XFRLEN2PHASEXWDLEN2XFRLEN1XWDLEN1 58 232414213031 7 Phase 2 Phase 1 16 20 2345BC

8. Chapter 6, Slide 8 Definitions - Review b1b2 CLK Word 1 Frame 1 Phase 2 Phase 1 FS SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port RFRLEN1RWDLEN158147XFRLEN1XWDLEN1 58 14 RFRLEN2RWDLEN2 23242130 XFRLEN2XWDLEN2 23242130 31 31 7 PHASE PHASE Phase 1 Phase 2 Frame 2 Word 2 Word 3

9. Chapter 6, Slide 9Objectives  Definition of Terms:  Bit, word or channel, frame and phase.  Understand basic serial port operation.  Understand clock generation.  Pin polarity.  Serial port interrupts.  Describe multi-channel operation.  Programming the serial port.

10. Chapter 6, Slide 10 McBSP Block Diagram (Read) CPU DMA PeripheralPeripheralBusBusPeripheralPeripheralBusBus RINTREVT RBRDRR 32 DR CLKR FSR RSR

11. Chapter 6, Slide 11 McBSP Block Diagram (Write) DX DXR CPU DMA PeripheralPeripheralBusBusPeripheralPeripheralBusBus RINT REVTRBRDRR 32 CLKX FSX DRCLKR FSR RSR XEVTXINTXSR

12. Chapter 6, Slide 12 McBSP Block Diagram (Configuration) RBRRSR DRR XSR DXR Multi-Channel Buffered Serial Port (McBSP) PeriphPeriphBusBusPeriphPeriphBusBus DR CLKRDX CLKX FSX CPUCPU DMADMA Peripheral Bus Serial Port Control Logic SPCR RCR XCR? ? FSR

13. Chapter 6, Slide 13 Serial Port - Basic Operation RBRRSR DRR XSR DXR Multi-Channel Buffered Serial Port (McBSP) PeriphPeriphBusBusPeriphPeriphBusBus DR CLKR FSR DXCLKX FSX CPU DMA “RECEIVE”“TRANSMIT” Peripheral Bus Serial Port Control Logic SPCR RCR XCRPCR SRGR

14. Chapter 6, Slide 14 McBSP Registers (1) RSRReceive Shift Reg RBRReceive Buffer Reg DRRData Receive Reg XSRTransmit Shift Reg DXRData Transmit Reg SPCRSerial Port Control Reg RCRReceive Control Reg XCRTransmit Control Reg Receive Transmit Control

15. Chapter 6, Slide 15Objectives  Definition of Terms:  Bit, word or channel, frame and phase.  Understand basic serial port operation.  Understand clock generation.  Pin polarity.  Serial port interrupts.  Describe multi-channel operation.  Programming the serial port.

16. Chapter 6, Slide 16 Configure CLK and FS as inputs or outputs  FSR, FSX, CLKR and CLKX can be configured either as inputs or outputs, depending on the application. Multi-Channel Buffered Serial Port (McBSP) CLKR CLKX FSR FSX Serial Port Control Logic SPCR RCR XCRPCR SRGR

17. Chapter 6, Slide 17 Configure CLK and FS as inputs or outputs Multi-Channel Buffered Serial Port (McBSP) CLKR CLKX FSR FSX Serial Port Control Logic SPCR RCR XCRPCR SRGR CLK/FS Mode 0: Input 1: Output SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port CLKRMFSRM 10 FSXM 11 CLKXM 8 9

18. Chapter 6, Slide 18 Generating CLK and FS as output ‘C6000 FSRFSX CLKRCLKX SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port CLKRMFSRM10FSXM 11 CLKXM89 CLK/FS Mode 0: Input 1: Output

19. Chapter 6, Slide 19 Generating the CLK as output ‘C6000 FSRFSX CLKRCLKX SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port CLKSM29 Sample Rate Generator (SRGR) CLKSMCLKOUT1CLKS   CLKGDV CLKG  CLKGDV - divide down (1-255)  CLKG = (input clock) / (1 + CLKGDV )  Max transfer rate = CLKG = 150 MHz/2 = 75 Mb/s  CLKSM - selects clock src ( CLKOUT1 or CLKS ) CLKGDV07

20. Chapter 6, Slide 20 Generating the FS as output ‘C6000 SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port FSRFSX CLKRCLKX Sample Rate Generator (SRGR) CLKSM   CLKGDV CLKG FPER FSG CLKSM 29 CLKGDV 0 7 FSGM 28 FWID 815 FPER 2716CLKOUT1CLKS  FPER: frame sync period (12 bits)  FWID:frame sync pulse width (8 bits)  FSGM: 0 - FS gen’d on every DXR XSR copy 1 - FS gen’d by FSG 

21. Chapter 6, Slide 21 McBSP Registers (2) RSRReceive Shift Reg RBRReceive Buffer Reg DRRData Receive Reg XSRTransmit Shift Reg DXRData Transmit Reg SPCRSerial Port Control Reg RCRReceive Control Reg XCRTransmit Control Reg SRGRSample Rate Generator Receive Transmit Control

22. Chapter 6, Slide 22Objectives  Definition of Terms:  Bit, word or channel, frame and phase.  Understand basic serial port operation.  Understand clock generation.  Pin polarity.  Serial port interrupts.  Describe multi-channel operation.  Programming the serial port.

23. Chapter 6, Slide 23 Configure CLK and FS pin polarity Multi-Channel Buffered Serial Port (McBSP) CLKR CLKX FSR FSX Serial Port Control Logic SPCR RCR XCRPCR SRGR CLK/FS Polarity 0: Falling edge 1: Rising Edge SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port CLKRPFSRP 2 FSXP 3 CLKXP 0 1

24. Chapter 6, Slide 24Objectives  Definition of Terms:  Bit, word or channel, frame and phase.  Understand basic serial port operation.  Understand clock generation.  Pin polarity.  Serial port status and interrupts.  Describe multi-channel operation.  Programming the serial port.

25. Chapter 6, Slide 25 RRDY/XRDY Status and Interrupts CPU RINTXINT EDMA Sync  RRDY/XRDY displays the “status” of the read and transmit ports: 0: not ready. 0: not ready. 1: ready to read/write. 1: ready to read/write. RBRDRR XSRDXR RRDY=1 XRDY=1 “Ready to Read” “Ready to Write” SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port RRDY 1 XRDY 17  There are 3 methods for detecting if data is ready: Poll SPCR bits via s/w. Poll SPCR bits via s/w. Config CPU ints (RINT/XINT). Config CPU ints (RINT/XINT). Program DMA sync events. Program DMA sync events.

26. Chapter 6, Slide 26 Other sources of Interrupts (R/XINT) CPU RINT XINT RRDY (RINTM=00b) End of Block (RCV) (RINTM=01) New FSR (frame begin) (RINTM=10b) Receive Sync Error (RINTM=11b) XRDY (XINTM=00b) End of Block (XMT) (XINTM=01b) New FSX (frame begin) (XINTM=10b) Transmit Sync Error (XINTM=11b) “Trigger Event” SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port RRDY 1 XRDY 17 XINTM 2021 RINTM 4 5

27. Chapter 6, Slide 27Objectives  Definition of Terms:  Bit, word or channel, frame and phase.  Understand basic serial port operation.  Understand clock generation.  Pin polarity.  Serial port status and interrupts.  Describe multi-channel operation.  Programming the serial port.

28. Chapter 6, Slide 28 Multi-Channel operation How do you enable/disable each channel? Ch0Ch1Ch31Ch0Ch1Ch31 DR/X FSR/X...

29. Chapter 6, Slide 29 Multi-Channel operation Ch0Ch1Ch31Ch0Ch1Ch31 DR/X FSR/X...  You can enable or disable any channel. Master (MCR) Rcv En (RCER) Xmt En (XCER) Multi-Channel RCER/XCER Enable Bits Enable[1] Disable[0] 031 031 RCER XCER 0111 … 0

30. Chapter 6, Slide 30 Memory 4321 Frame 3 Multi-channel example 1 3... 1 1 Frame 1 432 3 1432 Frame 2 1 3 Framer  Allows multiple channels (words) to be independently selected for transmit and receive. McBSP

31. Chapter 6, Slide 31  EDMA’s can sort each channel into separate buffers! Memory 4321 Frame 3 3 3... 1 1 Frame 1 432 1 1432 Frame 2 1 3 Framer McBSPEDMA Multi-channel and EDMA combination used for channel sorting

32. Chapter 6, Slide 32 Memory 4321 Frame 3 3 3... 1 1 Frame 1 432 1 1432 Frame 2 1 3 Framer McBSPEDMA EDMA Channel Sorting  EDMA’s flexible (indexed) addressing allows it to sort each channel into separate buffers!  How do you select channels?...

33. Chapter 6, Slide 33 Enable/Disable Channels Master (MCR) Rcv En (RCER) Xmt En (XCER) Multi-Channel 031031RCER XCER 0101 …  RCER / XCER registers allow you to enable or disable only 32-channels.  So how does the C6000 supports 128 channels?

34. Chapter 6, Slide 34 128 Channels! 0-1516-3132-4748-6364-7980-9596-111112-127ChannelsAB To be able to support 128 channels the following applies:  Channels are broken into BLOCK ’s (16 contiguous channels).  Up to 32 channels (2 BLOCK ’s) can be enabled at any one time.  Channels are enabled via _CER registers and _BLK bits in MCR.  After 16 channels, McBSP issues END_OF_BLOCK interrupt.  CPU ISR re-programs RCER (or XCER) for channels 32-47 and so on. Master (MCR) Rcv En (RCER) Xmt En (XCER) Multi-Channel 031031RCER XCER A 15-0 B 15-0 A 15-0 B 15-0 1516 1516 Interrupt

35. Chapter 6, Slide 35 McBSP Registers (3) RSRReceive Shift Reg RBRReceive Buffer Reg DRRData Receive Reg XSRTransmit Shift Reg DXRData Transmit Reg SPCRSerial Port Control Reg RCRReceive Control Reg XCRTransmit Control Reg SRGRSample Rate Generator PCRPin Control Reg Receive Transmit Control MCRMulti-Channel Ctrl Reg RCERRcv Channel Enable Reg XCERXmit Channel Enable Reg

36. Chapter 6, Slide 36Objectives  Definition of Terms:  Bit, word or channel, frame and phase.  Understand basic serial port operation.  Understand clock generation.  Pin polarity.  Serial port status and interrupts.  Describe multi-channel operation.  Programming the serial port.

37. Chapter 6, Slide 37 Programming the Serial Port  There are three methods available for programming the serial port: 1.Writing directly to the serial port registers. 2.Using the Chip Support Library (CSL). 3.Graphically using the DSP/BIOS GUI configuration tool.

38. Chapter 6, Slide 38 Programming the Serial Port - Direct (A)Writing directly to the serial port registers:  Although this method is straight forward, it relies on a good understanding of the serial port functionality.  This method can be tedious and is prone to errors. #include #include void mcbsp0_init() { *(unsigned volatile int *)McBSP0_SPCR = 0; *(unsigned volatile int *)McBSP0_PCR = 0; *(unsigned volatile int *)McBSP0_RCR = 0x10040; *(unsigned volatile int *)McBSP0_XCR = 0x10040; *(unsigned volatile int *)McBSP0_DXR = 0; *(unsigned volatile int *)McBSP0_SPCR = 0x12001; }

39. Chapter 6, Slide 39 Programming the Serial Port - CSL (1/4) (B)Using the Chip Support Library:  The CSL provides a C language interface for configuring and controlling the on-chip peripherals, in this case the Serial Ports.  The library is modular with each module corresponding to a specific peripheral. This has the advantage of reducing the code size.  Some modules rely on other modules also being included, for example the IRQ module is required when using the EDMA module.

40. Chapter 6, Slide 40  CSL programming procedure: (1)Create handles for the serial ports: (2)Open the serial port: Programming the Serial Port - CSL (1/4) MCBSP_Handle hMcbsp; hMcbsp = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);

41. Chapter 6, Slide 41  CSL programming procedure: (3)Create a configuration structure for serial port:  McBSP_Config_Struct.pdf McBSP_Config_Struct.pdf Programming the Serial Port - CSL (2/4)

42. Chapter 6, Slide 42 Programming the Serial Port - CSL (3/4)  CSL programming procedure (cont): (4)Configure the serial port: (5)Close the Serial Port after use: MCBSP_config(hMcbsp,&ConfigLoopback); MCBSP_close(hMcbsp);

43. Chapter 6, Slide 43 Programming the Serial Port - CSL (4/4) Practical example on DSP Code 6416  Project name: C6416_DSK_INOUT.pjt  Location: Lecture 6, Lab6

44. Chapter 6, Slide 44 Programming the Serial Port using the DSP/BIOS GUI (C)DSP/BIOS GUI Interface:  With this method the configuration structure is created graphically and the setup code is generated automatically.

45. Chapter 6, Slide 45  Procedure: (1)Create a configuration using the MCBSP Configuration manager (eg. mcbspCfg0). Programming the Serial Port using the DSP/BIOS GUI

46. Chapter 6, Slide 46 Programming the Serial Port using the DSP/BIOS GUI  Procedure: (2)Right click on mcbspCfg0 and select “Properties”, see figures below, and then select “Advanced” and fill all parameters as shown below:

47. Chapter 6, Slide 47 Programming the Serial Port using the DSP/BIOS GUI  Procedure: (3)Select the serial port you would like to use from the MCBSP Resource manager (eg. Mcbsp_Port1). Right click and select properties. Select the mcbspCfg0 configuration just created.

48. Chapter 6, Slide 48 Programming the Serial Port using the DSP/BIOS GUI  Procedure: (4)A file is then generated that contains the configuration code. The file generated for this example is shown on the next slide.

49. Chapter 6, Slide 49 Programming the Serial Port using the DSP/BIOS GUI /* Do *not* directly modify this file. It was */ /* generated by the Configuration Tool; any */ /* changes risk being overwritten. */ /* INPUT mcbsp1.cdb */ /* Include Header File */ #include "mcbsp1cfg.h" /* Config Structures */ MCBSP_Config mcbspCfg0 = { 0x00008000, /* Serial Port Control Reg. (SPCR) */ 0x000000A0, /* Receiver Control Reg. (RCR) */ 0x000000A0, /* Transmitter Control Reg. (XCR) */ 0x203F1F0F, /* Sample-Rate Generator Reg. (SRGR) */ 0x00000000, /* Multichannel Control Reg. (MCR) */ 0x00000000, /* Receiver Channel Enable(RCER) */ 0x00000000, /* Transmitter Channel Enable(XCER) */ 0x00000A00 /* Pin Control Reg. (PCR) */ }; /* Handles */ MCBSP_Handle hMcbsp1; /* * ======== CSL_cfgInit() ======== */ void CSL_cfgInit() { hMcbsp1 = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET); MCBSP_config(hMcbsp1, &mcbspCfg0); }

50. Chapter 6, Slide 50 Programming the Serial Port using the DSP/BIOS GUI Few remarks: (1) Notice that values in the code generated are the same as the values inserted using the GUI interface. /* Do *not* directly modify this file. It was */ /* Config Structures */ MCBSP_Config mcbspCfg0 = { 0x00008000, /* Serial Port Control Reg. (SPCR) */ 0x000000A0, /* Receiver Control Reg. (RCR) */ 0x000000A0, /* Transmitter Control Reg. (XCR) */ 0x203F1F0F, /* Sample-Rate Generator Reg. (SRGR) */ 0x00000000, /* Multichannel Control Reg. (MCR) */ 0x00000000, /* Receiver Channel Enable(RCER) */ 0x00000000, /* Transmitter Channel Enable(XCER) */ 0x00000A00 /* Pin Control Reg. (PCR) */ };

51. Chapter 6, Slide 51 Programming the Serial Port using the DSP/BIOS GUI Few remarks: (2) Do not forget to close the serial port after use. (3) To visualise the output of the logprintf () function make sure that the Message Log window is open (DSP/BIOS > Message Log).

52. Chapter 6, Slide 52 Programming the Serial Port - CSL (4/4) Practical example  Project name: mcbsp_staticcfg.pjt  Location: Lecture 06 - McBSP\Static_CSL_Config\  Extra Topic: Digital Loopback Digital Loopback Digital Loopback

53. Chapter 6 Multi-channel Buffered Serial Port (McBSP) - End -

54. Chapter 6, Slide 54 Digital Loopback (DLB) DRCLKRFSR FSXCLKXDX RCV XMT McBSP  Allows testing of the Serial Port code without the need of an external device.  Digital Loopback internally connects the rcv/xmt ports together as shown.  No hardware (pin connections) necessary.  Interrupts are generated as normal (as programmed).

55. Chapter 6, Slide 55 Digital Loopback (DLB)  You can set the digital loop back by setting a bit in the SPCR or graphically using the GUI interface as shown: SPCR03115DLB