1. © 2000 Morgan Kaufman Overheads for Computers as Components CPUs zInput and output. zSupervisor mode, exceptions, traps. zCo-processors.

2. © 2000 Morgan Kaufman Overheads for Computers as Components I/O devices zUsually includes some non-digital component. zTypical digital interface to CPU: CPU status reg data reg mechanism

3. © 2000 Morgan Kaufman Overheads for Computers as Components Application: 8251 UART zUniversal asynchronous receiver transmitter (UART) : provides serial communication. z8251 functions are integrated into standard PC interface chip. zAllows many communication parameters to be programmed.

4. © 2000 Morgan Kaufman Overheads for Computers as Components Serial communication zCharacters are transmitted separately: time bit 0bit 1bit n-1 no char start stop...

5. © 2000 Morgan Kaufman Overheads for Computers as Components Serial communication parameters zBaud (bit) rate. zNumber of bits per character. zParity/no parity. zEven/odd parity. zLength of stop bit (1, 1.5, 2 bits).

6. © 2000 Morgan Kaufman Overheads for Computers as Components 8251 CPU interface CPU 8251 status (8 bit) data (8 bit) serial port xmit/ rcv

7. © 2000 Morgan Kaufman Overheads for Computers as Components Programming I/O zTwo types of instructions can support I/O: yspecial-purpose I/O instructions; ymemory-mapped load/store instructions.  Intel x86 provides in, out instructions. Most other CPUs use memory-mapped I/O. zI/O instructions do not preclude memory- mapped I/O.

8. © 2000 Morgan Kaufman Overheads for Computers as Components ARM memory-mapped I/O zDefine location for device: DEV1 EQU 0x1000 zRead/write code: LDR r1,#DEV1 ; set up device adrs LDR r0,[r1] ; read DEV1 LDR r0,#8 ; set up value to write STR r0,[r1] ; write value to device

9. © 2000 Morgan Kaufman Overheads for Computers as Components SHARC memory mapped I/O zDevice must be in external memory space (above 0x400000). zUse DM to control access: I0 = 0x400000; M0 = 0; R1 = DM(I0,M0);

10. © 2000 Morgan Kaufman Overheads for Computers as Components Peek and poke zTraditional HLL interfaces: int peek(char *location) { return *location; } void poke(char *location, char newval) { (*location) = newval; }

11. © 2000 Morgan Kaufman Overheads for Computers as Components Busy/wait output zSimplest way to program device. yUse instructions to test when device is ready. current_char = mystring; while (*current_char != ‘\0’) { poke(OUT_CHAR,*current_char); while (peek(OUT_STATUS) != 0); current_char++; }

12. © 2000 Morgan Kaufman Overheads for Computers as Components Simultaneous busy/wait input and output while (TRUE) { /* read */ while (peek(IN_STATUS) == 0); achar = (char)peek(IN_DATA); /* write */ poke(OUT_DATA,achar); poke(OUT_STATUS,1); while (peek(OUT_STATUS) != 0); }

13. © 2000 Morgan Kaufman Overheads for Computers as Components Interrupt I/O zBusy/wait is very inefficient. yCPU can’t do other work while testing device. yHard to do simultaneous I/O. zInterrupts allow a device to change the flow of control in the CPU. yCauses subroutine call to handle device.

14. © 2000 Morgan Kaufman Overheads for Computers as Components Interrupt interface CPU status reg data reg mechanism PC intr request intr ack data/address IR

15. © 2000 Morgan Kaufman Overheads for Computers as Components Interrupt behavior zBased on subroutine call mechanism. zInterrupt forces next instruction to be a subroutine call to a predetermined location. yReturn address is saved to resume executing foreground program.

16. © 2000 Morgan Kaufman Overheads for Computers as Components Interrupt physical interface zCPU and device are connected by CPU bus. zCPU and device handshake: ydevice asserts interrupt request; yCPU asserts interrupt acknowledge when it can handle the interrupt.

17. © 2000 Morgan Kaufman Overheads for Computers as Components Example: character I/O handlers void input_handler() { achar = peek(IN_DATA); gotchar = TRUE; poke(IN_STATUS,0); } void output_handler() { }

18. © 2000 Morgan Kaufman Overheads for Computers as Components Example: interrupt-driven main program main() { while (TRUE) { if (gotchar) { poke(OUT_DATA,achar); poke(OUT_STATUS,1); gotchar = FALSE; }

19. © 2000 Morgan Kaufman Overheads for Computers as Components Example: interrupt I/O with buffers zQueue for characters: headtail headtail a

20. © 2000 Morgan Kaufman Overheads for Computers as Components Buffer-based input handler void input_handler() { char achar; if (full_buffer()) error = 1; else { achar = peek(IN_DATA); add_char(achar); } poke(IN_STATUS,0); if (nchars == 1) { poke(OUT_DATA,remove_char(); poke(OUT_STATUS,1); } }

21. © 2000 Morgan Kaufman Overheads for Computers as Components I/O sequence diagram :foreground:input:output:queue empty a b bc c

22. © 2000 Morgan Kaufman Overheads for Computers as Components Debugging interrupt code zWhat if you forget to change registers? yForeground program can exhibit mysterious bugs. yBugs will be hard to repeat---depend on interrupt timing.

23. © 2000 Morgan Kaufman Overheads for Computers as Components Priorities and vectors zTwo mechanisms allow us to make interrupts more specific: yPriorities determine what interrupt gets CPU first. yVectors determine what code is called for each type of interrupt. zMechanisms are orthogonal: most CPUs provide both.

24. © 2000 Morgan Kaufman Overheads for Computers as Components Prioritized interrupts CPU device 1device 2device n L1 L2.. Ln interrupt acknowledge

25. © 2000 Morgan Kaufman Overheads for Computers as Components Interrupt prioritization zMasking: interrupt with priority lower than current priority is not recognized until pending interrupt is complete. zNon-maskable interrupt (NMI): highest- priority, never masked. yOften used for power-down.

26. © 2000 Morgan Kaufman Overheads for Computers as Components Example: Prioritized I/O :interrupts:foreground:A:A:B:B:C:C B A,B C A

27. © 2000 Morgan Kaufman Overheads for Computers as Components Interrupt vectors zAllow different devices to be handled by different code. zInterrupt vector table: handler 0 handler 1 handler 2 handler 3 Interrupt vector table head

28. © 2000 Morgan Kaufman Overheads for Computers as Components Interrupt vector acquisition :CPU:device receive request receive ack receive vector

29. © 2000 Morgan Kaufman Overheads for Computers as Components Generic interrupt mechanism intr? N Y Assume priority selection is handled before this point. N ignore Y ack vector? Y Y N timeout? Y bus error call table[vector] intr priority > current priority? continue execution

30. © 2000 Morgan Kaufman Overheads for Computers as Components Interrupt sequence zCPU acknowledges request. zDevice sends vector. zCPU calls handler. zSoftware processes request. zCPU restores state to foreground program.

31. © 2000 Morgan Kaufman Overheads for Computers as Components Sources of interrupt overhead zHandler execution time. zInterrupt mechanism overhead. zRegister save/restore. zPipeline-related penalties. zCache-related penalties.

32. © 2000 Morgan Kaufman Overheads for Computers as Components ARM interrupts zARM7 supports two types of interrupts: yFast interrupt requests (FIQs). yInterrupt requests (IRQs). zInterrupt table starts at location 0.

33. © 2000 Morgan Kaufman Overheads for Computers as Components ARM interrupt procedure zCPU actions: ySave PC. Copy CPSR to SPSR. yForce bits in CPSR to record interrupt. yForce PC to vector. zHandler responsibilities: yRestore proper PC. yRestore CPSR from SPSR. yClear interrupt disable flags.

34. © 2000 Morgan Kaufman Overheads for Computers as Components ARM interrupt latency zWorst-case latency to respond to interrupt is 27 cycles: yTwo cycles to synchronize external request. yUp to 20 cycles to complete current instruction. yThree cycles for data abort. yTwo cycles to enter interrupt handling state.

35. © 2000 Morgan Kaufman Overheads for Computers as Components SHARC interrupt structure zInterrupts are vectored and prioritized. zPriorities are fixed: reset highest, user SW interrupt 3 lowest. zVectors are also fixed. Vector is offset in vector table. Table starts at 0x20000 in internal memory, 0x40000 in external memory.v

36. © 2000 Morgan Kaufman Overheads for Computers as Components SHARC interrupt sequence Start: must be executing or IDLE/IDLE16. 1. Output appropriate interrupt vector address. 2. Push PC value onto PC stack. 3. Set bit in interrupt latch register. 4. Set IMASKP to current nesting state.

37. © 2000 Morgan Kaufman Overheads for Computers as Components SHARC interrupt return Initiated by RTI instruction. 1. Return to address at top of PC stack. 2. Pop PC stack. 3. Pop status stack if appropriate. 4. Clear bits in interrupt latch register and IMASKP.

38. © 2000 Morgan Kaufman Overheads for Computers as Components SHARC interrupt performance Three stages of response: y1 cycle: synchronization and latching; y1 cycle: recognition; y2 cycles: brancing to vector. Total latency: 3 cycles. Multiprocessor vector interrupts have 6 cycle latency.

39. © 2000 Morgan Kaufman Overheads for Computers as Components Supervisor mode zMay want to provide protective barriers between programs. yAvoid memory corruption. zNeed supervisor mode to manage the various programs. zSHARC does not have a supervisor mode.

40. © 2000 Morgan Kaufman Overheads for Computers as Components ARM supervisor mode zUse SWI instruction to enter supervisor mode, similar to subroutine: SWI CODE_1 zSets PC to 0x08. zArgument to SWI is passed to supervisor mode code. zSaves CPSR in SPSR.

41. © 2000 Morgan Kaufman Overheads for Computers as Components Exception zException: internally detected error. zExceptions are synchronous with instructions but unpredictable. zBuild exception mechanism on top of interrupt mechanism. zExceptions are usually prioritized and vectorized.

42. © 2000 Morgan Kaufman Overheads for Computers as Components Trap zTrap (software interrupt): an exception generated by an instruction. yCall supervisor mode. zARM uses SWI instruction for traps. zSHARC offers three levels of software interrupts. yCalled by setting bits in IRPTL register.

43. © 2000 Morgan Kaufman Overheads for Computers as Components Co-processor zCo-processor: added function unit that is called by instruction. yFloating-point units are often structured as co-processors. zARM allows up to 16 designer-selected co- processors. yFloating-point co-processor uses units 1 and 2.