1. Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 28: November 7, 2014 Memory Overview

2. Today Memory –Motivation –Organization –Basic components –Optimization concerns Project 2 is on this Penn ESE370 Fall2014 -- DeHon 2

3. Know how to store state Penn ESE370 Fall2014 -- DeHon 3

4. Register Storage Could just put together a large number of registers Concerns? Penn ESE370 Fall2014 -- DeHon 4

5. Concerns? Large number of wires –Could determine area –5 wire pitch  how wide? May want to store for many cycles Penn ESE370 Fall2014 -- DeHon 5

6. Usage Scenario How many state values read on each cycle? Penn ESE370 Fall2014 -- DeHon 6

7. Concerns? Large number of wires –Could determine area May want to store for many cycles Not able to update all on every cycle Not able to use all on every cycle Penn ESE370 Fall2014 -- DeHon 7

8. Limited Data Use What else do we need to share the wires if can only use one register on each cycle? –Use with shared data path Need to select the one output –Can only update one Need to control which one gets written Penn ESE370 Fall2014 -- DeHon 8

9. Limited Data Use Add load enable to register Logic to enable one register on write Mux to select output Penn ESE370 Fall2014 -- DeHon 9 we

10. Good Solution? Could get away with just latch –Not full register with master/slave latch Pay large amount for decode and mux –Proportional to memory bits Penn ESE370 Fall2014 -- DeHon 10 we

11. Memory Idea Maximize storage density (bits/cm 2 ) By minimizing the size/complexity of the repeated element Use shared periphery circuits to provide full functionality Trades off bandwidth (concurrent access) to save area Penn ESE370 Fall2014 -- DeHon 11

12. Memory Bank Penn ESE370 Fall2014 -- DeHon 12

13. Tristate Driver Penn ESE370 Fall2014 -- DeHon 13

14. Tri-State Drivers Penn ESE370 Fall2014 -- DeHon 14

15. Share Address Decode Word – group of bits read/written together –All have same control Penn ESE370 Fall2014 -- DeHon 15 (explored address decoder on midterm2)

16. Share Address Decode Words Mux select bits (words) from row read –When only want a subset Penn ESE370 Fall2014 -- DeHon 16

17. Share Address Decode Result: only spend N 0.5 area (perimeter) on selecting rather than linear in bits Penn ESE370 Fall2014 -- DeHon 17

18. Gate Density When is 14n > 5n+32*sqrt(n) ? Penn ESE370 Fall2014 -- DeHon 18

19. Memory Row Use shared enable for wire economy –Word line Penn ESE370 Fall2014 -- DeHon 19

20. Memory Column Use shared bus for area and wire economy –Row enable selects the cells to read/write from bus Penn ESE370 Fall2014 -- DeHon 20

21. Memory Cell Hold data Conditionally drive onto output bus Conditionally overwritten with data from bus Penn ESE370 Fall2014 -- DeHon 21

22. 5T SRAM Memory Bit Penn ESE370 Fall2014 -- DeHon 22

23. Penn ESE370 Fall2014 -- DeHon 23 SRAM Memory bit Core is back-to-back inverters for storage

24. Penn ESE370 Fall2014 -- DeHon 24 SRAM Memory bit Pass gate mux for output to column –Bit-Line (BL)

25. Penn ESE370 Fall2014 -- DeHon 25 SRAM Memory bit How do we write into this cell? –No directionality to pass gate –If drive BL strong enough, can flip value in selected cell Ratioed operation

26. Column Capacitance What is capacitance of bit line (column)? –W access – transistor width of column device –d rows –  =C diff /C gate Penn ESE370 Fall2014 -- DeHon 26

27. Time Driving Bit Line In terms of W access, W buf, d For W access =W buf =1, d=512,  =0.5 Penn ESE370 Fall2014 -- DeHon 27

28. Column Capacitance Consequence Want W access, W buf small to keep memory cell small Increasing W access, also increases C bl –Don’t really win by sizing up Conclude: Driving bit line will be slow Penn ESE370 Fall2014 -- DeHon 28

29. Column Sensing Speedup read time by sensing limited swing Sense circuit detects small change in bit line voltage –Precharge to intermediate voltage Amplifier for output Penn ESE370 Fall2014 -- DeHon 29

30. Output Amps Bottom of array includes Sense Amplifiers from bit lines to output Penn ESE370 Fall2014 -- DeHon 30

31. Column Write Writes driven from outside array Use large driver –Strong enough to flip memory bit –Strong so can charge column quickly Penn ESE370 Fall2014 -- DeHon 31

32. Column Write Writes driven from outside array Use large driver –Strong enough to flip memory bit –Strong so can charge column quickly Disable when not write –Be careful on your project2 –Could overwrite wrong row Penn ESE370 Fall2014 -- DeHon 32

33. Complete Memory Bank Penn ESE370 Fall2014 -- DeHon 33

34. Idea Memory for compact state storage Share circuitry across many bits –Minimize area per bit  maximize density Aggressively use: –Pass transistors, Ratioing –Precharge, Amplifiers to keep area down Penn ESE370 Fall2014 -- DeHon 34

35. Admin HW7 due Tuesday MT2 solutions posted Penn ESE370 Fall2014 -- DeHon 35