1. 113 January 2005Antoine Junique / CERN - PH NEW RCU LAYOUT CERN, 13 January 2005 Content  BOARD FLOORPLAN  PCB LAYERS  PCB STACKUP

2. 213 January 2005Antoine Junique / CERN - PH PCB FLOORPLAN TOP SIDE VOLTAGE REGULATORS PWR CONNECTOR DCS CONNECTORS SIU CONNECTORS

3. 313 January 2005Antoine Junique / CERN - PH PCB FLOORPLAN BOTTOM SIDE MAIN FPGA (XC2VP4) AUX FPGA (MAXII) FLASH MEM GTLP TRANSCEIVERS) BACKPLANE CONNECTORS CLK PECL TRX

4. 413 January 2005Antoine Junique / CERN - PH PCB LAYERS TOP LAYER

5. 513 January 2005Antoine Junique / CERN - PH PCB LAYERS LAYER L2 GROUND

6. 613 January 2005Antoine Junique / CERN - PH PCB LAYERS LAYER L3

7. 713 January 2005Antoine Junique / CERN - PH PCB LAYERS LAYER L4 1.5V FPGA CORE 1.5V GTL A (INT)1.5V GTL A (EXT) 1.5V GTL B (INT)1.5V GTL B (EXT) PRIMARY 3.3V PRIMARY 4.3V

8. 813 January 2005Antoine Junique / CERN - PH PCB LAYERS LAYER L5 3.3V

9. 913 January 2005Antoine Junique / CERN - PH PCB LAYERS LAYER L6

10. 1013 January 2005Antoine Junique / CERN - PH PCB LAYERS LAYER L7 GROUND

11. 1113 January 2005Antoine Junique / CERN - PH PCB LAYERS LAYER L8

12. 1213 January 2005Antoine Junique / CERN - PH PCB STACKUP RCU4 – Class 6 Printed Circtui Board Stack-Up (8 conductive layers PCB – total thickness 1680  m)