1. 1 Advanced Digital Design Reconfigurable Logic by A. Steininger and M. Delvai Vienna University of Technology

2. 2 Outline Introduction Introduction Reconfigurable Logic Issues Reconfigurable Logic Issues Conclusion Conclusion

3. 3 … in the `40s Problem: How can we use the same hardware platform for different applications ? Answer: Microcontroller concept: Map each application to the same instruction set This is an extremly flexible, but also an ineffiecient approach

4. 4 A New Paradigm Reconfigurable hardware allows to tailor the same hardware to individual applications „on the fly“:  Techniques used for software development can be applied to hardware  Problem specific circuits allows highly efficient computations Key technology  FPGA

5. 5 FPGA (1) Programmable logic elements Programmable logic elements Programmable interconnects Programmable interconnects LE programmable switch matrix

6. 6 Configuration memory FPGA (2) Resulting circuit LE Inputs Outputs Configuration memory is SRAM based:  „fast“ reconfiguration  multiple reconfigurations possible ( > 100.000)

7. 7 Reconfigurable Logic Issues What Why Who When

8. 8 Reconfigurable Logic Issues WhenWhat WhoWhy

9. 9 Reconfigurable Logic Issues When does the reconfiguration take place ?  Once (at start-up)  Run-time reconfiguration  reconfiguration is performed during normal operation  During operation  Offline reconfiguration  operation stops  new configuration is loaded  operation continues

10. 10 Reconfigurable Logic Issues WhatWhen WhoWhy

11. 11 What is reconfigured Configuration memory Configuration memory LE cfg data LE 1) Entire FPGA Configuration memory Configuration memory cfg data LE 2) Parts of the FPGA LE 3) Multi-context reconfiguration Configuration memory LE cfg data Configuration memory LE

12. 12 Reconfigurable Logic Issues Who WhenWhat Why

13. 13 Who reconfigures One central controller One central controller External External New configuration can be „downloaded“ from outside Internal Internal Internal controller calculates and executes the configuration Distributed „controller“ Distributed „controller“ Intelligent Intelligent Each part of the system can decide on the need for rearrangement. Unintelligent Unintelligent Reconfiguration takes place according predifined rule in response to external events

14. 14 Reconfigurable Logic Issues Why WhenWhat Who

15. 15  Rapid Prototyping Why Reconfiguration

16. 16 Rapid Prototyping (1) First transistor (1947) Discrete devices (Mailüfterl,1958) TTL circuits -> 7400 Series (197x) Programmable Logic Devices (PLD) PLA, PAL, CPLD => Antifuse, (E)EPROM Gate Arrays -> customization only in the last fabrication step Field Programmable Gate Arrays (FPGAs)

17. 17 Rapid Prototyping (2) Advantage of FPGA: Short design cycles Reduce costs Design space exploration Valuable prototypes Suitable for small number of pieces Hardcopy …

18. 18  Rapid Prototyping  Save Logic Elements Why Reconfiguration

19. 19 Save Logic Elements (1) Time sharing: Programmable logic can be used to implement different modules in a device Time sharing: Programmable logic can be used to implement different modules in a device Example: Mobile phone Example: Mobile phone Virtualization: Programmable logic is used to „provide“ an infinite amount of logic Virtualization: Programmable logic is used to „provide“ an infinite amount of logic Compare: Physical and virtual memory Compare: Physical and virtual memory

20. 20 Virtual Hardware: The PipeRench Example (1) 1 1 5 5 4 4 3 3 2 2 Virtual Circuit Cycle1234567Stage1 Stage2 Stage3 cfg1 cfg2 cfg3 exe1 exe2 Mapping: 5 → 3 Pipestages Stage1 ? ? ? ? ? ? Physical Circuit Stage2 Stage3 cfg4 cfg5 cfg1 cfg2exe4 exe3 exe4 exe3 exe2 exe5 exe1 Principle: cfg … configuration exe … execution

21. 21 Virtual Hardware: The PipeRench Example(2) Advantages: Implementation of large virtual circuit in small physical devices Implementation of large virtual circuit in small physical devices Scalable performance Scalable performanceLimitations: Cycle dependency must fit in one pipeline stage Cycle dependency must fit in one pipeline stage Configuration must be performed in one clock cycle Configuration must be performed in one clock cycle

22. 22  Rapid Prototyping  Save Logic Elements  Improve Performance Why Reconfiguration

23. 23 Improve Performance Application specifics circuits Application specifics circuits Data driven computation Data driven computation Partial reconfiguration Partial reconfiguration (Soft)-CPU CI 1) (Soft)-CPU + Configurable Instructions 2) (Soft)-CPU + Configurable CoProcessor C-CoP Hardware Context Switch Hardware Context Switch

24. 24 Configuration Memory Configuration Memory Several configurations in the config memory Hardware Context Switch Task A Configuration Memory LE Inputs Outputs Static Task A.1Task A.2Task A.3CSW Context switching time

25. 25  Rapid prototyping  Save logic elements  Improve performance  Increase fault tolerance / self- healing circuits Why Reconfiguration

26. 26 Increase fault tolerance (1) Spare programmable logic replace faulty compoments Spare programmable logic replace faulty compoments Requirements Error detection Error detection Diagnosis Diagnosis Replacement strategy Replacement strategy Recovery RecoveryParameters: Block size Block size Detection delay Detection delay Recovery time Recovery time Overhead Overhead

27. 27 Increase fault tolerance (2) Examples: Examples: FPGA based TMR FPGA based TMR Column based precompiled configuration technique Column based precompiled configuration technique Function A Col1 Function B Col2 Function C Col3 Function D Col4 Unused Col5 Function A Col1 Function B Col2 Function C Col4 Function D Col5 Unused Col3 Limited changes  simple rerouting

28. 28 Increase fault tolerance (3) Example: Example: FPGA based TMR FPGA based TMR Coloum based precompiled configuration technique Coloum based precompiled configuration technique Fine-grained self healing hardware Fine-grained self healing hardware Inputs LUT k k k k k k Outputs LUT k k k k k k k XOR Fault Flag

29. 29 Global Challenges in Reconfigurable Computing Time required for reconfiguration Time required for reconfiguration Overhead for reconfigurability Overhead for reconfigurability Block size Block size Configuration data: Configuration data: Precompiled modules -> memory overhead Precompiled modules -> memory overhead Run time generated modules–> additional (intelligent) controller Run time generated modules–> additional (intelligent) controller Software tools Software tools

30. 30 Conclusion Reconfigurable logic changes the traditional way to implement digital systems: Reconfigurable logic changes the traditional way to implement digital systems: Hardware is becoming flexible as software Hardware is becoming flexible as software Arbitrarily combination of methodes presented in section „When, What, Who, Why“ Arbitrarily combination of methodes presented in section „When, What, Who, Why“ …