1. 1 November 11, 2015 The Evolution of Memory Architecture November 11, 2015 Dr. Amit Berman Senior Engineer, Samsung

2. 2 November 11, 2015 Legal Disclaimer This presentation is intended to provide information concerning SSD and memory industry. We do our best to make sure that information presented is accurate and fully up-to-date. However, the presentation may be subject to technical inaccuracies, information that is not up-to-date or typographical errors. As a consequence, Samsung does not in any way guarantee the accuracy or completeness of information provided on this presentation. The information in this presentation or accompanying oral statements may include forward- looking statements. These forward-looking statements include all matters that are not historical facts, statements regarding the Samsung Electronics' intentions, beliefs or current expectations concerning, among other things, market prospects, growth, strategies, and the industry in which Samsung operates. By their nature, forward-looking statements involve risks and uncertainties, because they relate to events and depend on circumstances that may or may not occur in the future. Samsung cautions you that forward looking statements are not guarantees of future performance and that the actual developments of Samsung, the market, or industry in which Samsung operates may differ materially from those made or suggested by the forward-looking statements contained in this presentation or in the accompanying oral statements. In addition, even if the information contained herein or the oral statements are shown to be accurate, those developments may not be indicative developments in future periods.

3. 3 November 11, 2015 Memory Hierarchy CPU SSD PCH IMC DIMM CACHE

4. 4 November 11, 2015 Memory Hierarchy CPU SSD PCH IMC DIMM CACHE SRAM pSec,MB DRAM nSec,GB Flash μSec,TB

5. 5 November 11, 2015 Memory System 0 External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Memory Module Comp. & Enc.

6. 6 November 11, 2015 Figures of Merit 0 External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Comp. & Enc.

7. 7 November 11, 2015 Figures of Merit 0 External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Comp. & Enc.

8. 8 November 11, 2015 Device Material – floating gate transistor, charge trap, phase-change, ReRAM, STT-MRAM Scaling – Cost of making smaller feature size Multi-bit per cell – Increases density and reduces performance

9. 9 November 11, 2015 Device Material – floating gate transistor, charge trap, phase-change, ReRAM, STT-MRAM Scaling – Cost of making smaller feature size Multi-bit per cell – Increases density and reduces performance Trend: CT Trend: slow lithography steps Trend: higher BPC

10. 10 November 11, 2015 Figures of Merit 0 External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Comp. & Enc.

11. 11 November 11, 2015 Figures of Merit 0 External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Array Architecture Comp. & Enc.

12. 12 November 11, 2015 Array Architecture NOR – Fast access to each cell, but low density NAND – High density, but slow performance (have to precharge and evaluate bitline) Vertical 3D / Cross-Point – Higher density than NAND and performance challenges

13. 13 November 11, 2015 Array Architecture NOR – Fast access to each cell, but low density NAND – High density, but slow performance (have to precharge and evaluate bitline) Vertical 3D / Cross-Point – Higher density than NAND and performance challenges Trend: RAM close to processor Trend: Multi-Layer far form processor

14. 14 November 11, 2015 Figures of Merit 0 External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Array Architecture Comp. & Enc.

15. 15 November 11, 2015 Figures of Merit 0 External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Array Architecture Access Organization Comp. & Enc.

16. 16 November 11, 2015 Access Organization # of Planes/Banks – More planes increase (part of) parallel instruction execution, but reduce bit density (area penalty) Wordline Size – Longer wordline increases write performance due to simultaneous access to more cells, but worsen read latency due to increased IR drop and inter-bitline coupling

17. 17 November 11, 2015 Access Organization # of Planes/Banks – More planes increase (part of) parallel instruction execution, but reduce bit density (area penalty) Wordline Size – Longer wordline increases write performance due to simultaneous access to more cells, but worsen read latency due to increased IR drop and inter-bitline coupling Trend: Slow increase Trend: Slow increase

18. 18 November 11, 2015 Figures of Merit 0 External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Array Architecture Access Organization Comp. & Enc.

19. 19 November 11, 2015 Figures of Merit 0 External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Array Architecture Access Organization Modulation & Preprocessing Comp. & Enc.

20. 20 November 11, 2015 Modulation Techniques DTA/ATD conversion – Transforming data to cell level (ISPP, Sensing) Data pre-processing – Algorithms that acquire soft device characteristics

21. 21 November 11, 2015 Modulation Techniques DTA/ATD conversion – Transforming data to cell level (ISPP, Sensing) Data pre-processing – Algorithms that acquire soft device characteristics Trend: increased complexity Trend: increased complexity

22. 22 November 11, 2015 Figures of Merit 0 External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Array Architecture Access Organization Modulation & Preprocessing Comp. & Enc.

23. 23 November 11, 2015 Figures of Merit 0 External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Array Architecture Access Organization Modulation & Preprocessing Reliability Algorithm Comp. & Enc.

24. 24 November 11, 2015 Reliability Algorithm ECC – Longer codewords lead to better correction capability but reduce read performance Signal Processing – Estimation and movement of reference voltage for sensing

25. 25 November 11, 2015 Reliability Algorithm ECC – Longer codewords lead to better correction capability but reduce read performance Signal Processing – Estimation and movement of reference voltage for sensing Trend: next step of LDPC Trend: increased estimation complexity

26. 26 November 11, 2015 Figures of Merit 0 Comp. & Enc. External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Array Architecture Access Organization Modulation & Preprocessing Reliability Algorithm

27. 27 November 11, 2015 Figures of Merit 0 Comp. & Encr. External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Array Architecture Access Organization Modulation & Preprocessing Reliability Algorithm Reduction & Security

28. 28 November 11, 2015 Data Reduction & Security Algorithms Compression and Deduplication – Performance-constrained low area compression and deduplication Encryption – Standard AES

29. 29 November 11, 2015 Data Reduction & Security Algorithms Compression and Deduplication – Performance-constrained low area compression and deduplication Encryption – Standard AES Trend: Conventional AES Trend: Advanced Constrained Compressor

30. 30 November 11, 2015 Figures of Merit 0 Comp. & Encr. External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Array Architecture Access Organization Modulation & Preprocessing Reliability Algorithm Reduction & Security

31. 31 November 11, 2015 Figures of Merit 0 Comp. & Encr. External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Array Architecture Access Organization Modulation & Preprocessing Reliability Algorithm Reduction & Security System Management

32. 32 November 11, 2015 System Algorithms Scheduling – Instruction assignment according to workload Wear Leveling – Block level statistics, L2P table management Interface – SATA, eSATA, SAS, PCIe, NVMe, eMMC, UFS

33. 33 November 11, 2015 System Algorithms Scheduling – Instruction assignment according to workload Wear Leveling – Block level statistics, L2P table management Interface – SATA, eSATA, SAS, PCIe, NVMe, eMMC, UFS Trend: High-Q balancing Trend: Conventional WL Trend: Migration to NVMe/UFS

34. 34 November 11, 2015 Figures of Merit 0 Comp. & Encr. External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Array Architecture Access Organization Modulation & Preprocessing Reliability Algorithm Reduction & Security System Management

35. 35 November 11, 2015 Putting it all together 0 Comp. & Encr. External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Array Architecture Access Organization Modulation & Preprocessing Reliability Algorithm Reduction & Security System Management

36. 36 November 11, 2015 Putting it all together 0 Comp. & Encr. External Controller WL BL DEC Buffer 00 AnalogControl Logic Management ECC & SP Device Array Architecture Access Organization Modulation & Preprocessing Reliability Algorithm Reduction & Security System Management

37. 37 November 11, 2015 Summary Device : CT MLC+ Architecture : 3D/Cross-Point Organization : WL+, #P+ Modulation : Device-Aware ISPP/Sensing ECC : LDPC+ Compression : Constrained Compressor Management: Large queue NVMe/UFS

38. 38 November 11, 2015 Q&A Session Thank You