1. Technical University Tallinn, ESTONIA 1 Raimund Ubar TTÜ raiub@pld.ttu.ee www.ttu.ee/ˇraiub/ Tallinn, 21. mai 2003 Kuidas tagada kvaliteeti üha keerukamates digitaalsüsteemides

2. Technical University Tallinn, ESTONIA 2 Outline Introduction to Digital Test Test as the quality problem Defect and fault models Hierarchical approach to test Decision Diagrams (beyond BDDs) Overview of tools developed at D&T Lab Conclusions

3. Technical University Tallinn, ESTONIA 3 Introduction Dependability Fault-Tolerance BIST Fault Diagnosis Test Reliability Security Safety There is no sequrity on the earth, there is only oportunity Douglas McArthur (General) Test Diagnosis Design for testability: Environment System Redesign if the testability is low

4. Technical University Tallinn, ESTONIA 4 Introduction – Test Tools Test System Fault dictionary System model Test generation Fault simulation Test result Fault diagnosis Go/No go Located defect Test experiment Test tools

5. Technical University Tallinn, ESTONIA 5 Introduction – Test Generation A fault a/0 is sensitisized by the value 1 on a line a A test t = 1101 is simulated, both without and with the fault a/0 The fault is detected since the output values in the two cases are different A path from the faulty line a is sensitized (bold lines) to the primary output Structural gate-level testing: fault sensitization:

6. Technical University Tallinn, ESTONIA 6 Introduction – Fault Simulation Parallel pattern simulation Fault-free circuit: Faulty circuit: & 1 x1x1 x2x2 x3x3 z y 001 101 001 010 011 & 1 x1x1 x2x2 x3x3 z y 001 101 111 010 111 Inserted stuck-at-1 fault Detected error Parallel fault simulation & 1 x1x1 x2x2 x3x3 z y 000 111 0 1 0 000 010 Stuck-at-0 Stuck-at-1 Computer word Fault-free Detected error Inserted faults

7. Technical University Tallinn, ESTONIA 7 Introduction – Fault Diagnosis 0110 T 6 0010011 FaultF 5 located FaultsF 1 andF 4 are not distinguishable Fault localization by fault tables No match, diagnosis not possible Fault table:Testing results:

8. Technical University Tallinn, ESTONIA 8 Test as the Quality Problem Quality policy Yield (Y) P,n Defect level Design for testability Testing P - probability of a defect n - number of defects - probability of producing a good product

9. Technical University Tallinn, ESTONIA 9 Test as the Quality Problem DL T(%) YY 1000 1 Y(%) T(%) 10 50 90 5090 851 45255 81459 DL   T  Paradox: Testability   DL  Improving the yield - DL  Y  - Test should be improved

10. Technical University Tallinn, ESTONIA 10 How Much to Test? Cost of testing Quality Cost of quality Cost Cost of the fault 100% 0% Optimum test / quality How to succeed? Try too hard! How to fail? Try too hard! (From American Wisdom) Conclusion: “The problem of testing can only be contained not solved” T.Williams

11. Technical University Tallinn, ESTONIA 11 How Much to Test? Paradox: 2 64 input patterns (!) for 32-bit accumulator will be not enough. A short will change the circuit into sequential one, and you will need because of that 2 65 input patterns Paradox: Mathematicians counted that Intel 8080 needed for exhaustive testing 37 (!) years Manufacturer did it by 10 seconds Majority of functions will never activated during the lifetime of the system Time can be your best friend or your worst enemy (Ray Charles) & & x1x1 x2x2 x3x3 y State q Y = F(x 1, x 2, x 3,q) * 1 1 Y = F(x 1, x 2, x 3 ) Bridging fault 0

12. Technical University Tallinn, ESTONIA 12 How to Generate a Good Test? Paradox: To generate a test for a block in a system, the computer needed 2 days and 2 nights An engineer did it by hand with 15 minutes So, why computers? The best place to start is with a good title. Then build a song around it. (Wisdom of country music) System 16 bit counter & 1 Sequence of 2 16 bits Sea of gates

13. Technical University Tallinn, ESTONIA 13 Complexity vs. Quality Problems: Traditional low-level test generation and fault simulation methods and tools for digital systems have lost their importance because of the complexity reasons Traditional Stuck-at Fault (SAF) model does not quarantee the quality for deep-submicron technologies How to improve test quality at increasing complexities of today's systems? Two main trends: –Defect-oriented test and –High-level modelling Both trends are caused by the increasing complexities of systems based on deep-submicron technologies

14. Technical University Tallinn, ESTONIA 14 Towards Solutions The complexity is handled by raising the abstraction levels from gate to RTL, ISA or behavioral levels –But this moves us even more away from the real life of defects (!) To handle defects in deep-submicron technologies, new defect- oriented fault models and test methods should be used –But, this is increasing even more the complexity (!) As a promising compromise and solution is: To combine hierarchical approach with defect orientation

15. Technical University Tallinn, ESTONIA 15 Outline Introduction to Digital Test Test as the quality problem Defect and fault models Hierarchical approach to test Decision Diagrams (beyond BDDs) Overview of tools developed at D&T Lab Conclusions

16. Technical University Tallinn, ESTONIA 16 Fault and defect modeling Defects, errors and faults An instance of an incorrect operation of the system being tested is referred to as an error The causes of the observed errors may be design errors or physical faults - defects Physical faults do not allow a direct mathematical treatment of testing and diagnosis The solution is to deal with fault models System Component Defect Error Fault

17. Technical University Tallinn, ESTONIA 17 Fault and defect modeling Why logic fault models? complexity of simulation reduces (many physical faults may be modeled by the same logic fault) one logic fault model is applicable to many technologies logic fault tests may be used for physical faults whose effect is not completely understood they give a possibility to move from the lower physical level to the higher logic level 1 x2x2 x1x1 Broken line 1 x2x2 x1x1 Bridge to ground 0V Single model: Stuck-at-0 Two defects: Stuck-at fault model: Test generation:

18. Technical University Tallinn, ESTONIA 18 Transistor Level Faults Stuck-at-1 Broken (change of the function) Bridging Stuck-open  New State Stuck-on (change of the function) Short (change of the function) Stuck-off (change of the function) Stuck-at-0 SAF-model is not able to cover all the transistor level defects How to model transistor defects ?

19. Technical University Tallinn, ESTONIA 19 Mapping Transistor Defects to Logic Level Short x1x1 x2x2 x3x3 x4x4 x5x5 y Generic function with defect: Function: Faulty function: A transistor fault causes a change in a logic function not representable by SAF model Defect variable: d =d = 0 – defect d is missing 1 – defect d is present For defects: For stuck-at-faults: Test generation: Defects are mapped from physical to the logic level

20. Technical University Tallinn, ESTONIA 20 Mapping Transistor Faults to Logic Level Short x1x1 x2x2 x3x3 x4x4 x5x5 y Test calculation by Boolean derivative: Generic function with defect: Function: Faulty function:

21. Technical University Tallinn, ESTONIA 21 Functional Fault vs. Stuck-at Fault No Full SAF-TestTest for the defect x1x1 x2x2 x3x3 x4x4 x5x5 x1x1 x2x2 x3x3 x4x4 x5x5 1 1110-10-01 2 0--111-001 3 0110101110 4 10110 5 1100- Full 100% Stuck-at-Fault-Test is not able to detect the short: The full SAF test is not covering any of the patterns able to detect the given transistor defect  Functional fault

22. Technical University Tallinn, ESTONIA 22 Generalization: Functional Fault Model Constraints calculation: y Component F(x 1,x 2,…,x n ) Defect WdWd Component with defect: Logical constraints Fault-free Faulty Fault model: (dy,W d ), (dy,{W k d }) Constraints: d = 1, if the defect is present

23. Technical University Tallinn, ESTONIA 23 Fault Table: Mapping Defects to Faults Diagnostic info for a complex gate AB&CD:

24. Technical University Tallinn, ESTONIA 24 Outline Introduction to Digital Test Test as the quality problem Defect and fault models Hierarchical approach to test Decision Diagrams (beyond BDDs) Overview of tools developed at D&T Lab Conclusions

25. Technical University Tallinn, ESTONIA 25 First Step to Quality How to improve the test quality at the increasing complexity of systems? First step to solution: Functional fault model was introduced as a means for mapping physical defects from the transistor or layout level to the logic level System Component Low level k WFkWFk WSkWSk Environment Bridging fault Mapping High level

26. Technical University Tallinn, ESTONIA 26 Faults and Test Generation Hierarchy Circuit Module System Network of gates Gat e Functional approach F ki Test F k W F ki W S F Test W F k W S k Structural approach Network of modules W d ki Interpretation of W F k : - as a test on the lower level - as a functional fault on the higher level Higher Level Component Lower level k WFkWFk WSkWSk Environment Bridging fault

27. Technical University Tallinn, ESTONIA 27 Hierarchical Test Generation Approaches Bottom-up approach: Pre-calculated tests for components generated on low-level will be assembled at a higher level It fits well to the uniform hierarchical approach to test, which covers both component testing and communication network testing However, the bottom-up algorithms ignore the incompleteness problem The constraints imposed by other modules and/or the network structure may prevent the local test solutions from being assembled into a global test The approach would work well only if the the corresponding testability demands were fulfilled A B C D a D c Local test: A = a.x B = f’(D) C = c.x a,c,D fixed x - free a System Module c

28. Technical University Tallinn, ESTONIA 28 Hierarchical Test Generation Approaches Top-down approach - to solve the test generation problem by deriving environmental constraints for low-level solutions. This method is more flexible, since it does not narrow the search for the global test solution to pregenerated patterns for the system modules The method is of little use when the system is still under development in a top-down fashion, or when “canned” local tests for modules or cores have to be applied Top-down approach: A B C D’ a’.x d’.x c’.x Symbolic global test: A = a’.x D’ = d’.x C = c’.x a’ c’ a’,c’,D’ fixed x - free System Module

29. Technical University Tallinn, ESTONIA 29 Two trends: high-level modeling –to cope with complexity low-level modeling –to cope with physical defects, to reach higher acuracy Hierarchical Diagnostic Modeling Boolean differential algebra BDD-s High-Level DD-s

30. Technical University Tallinn, ESTONIA 30 Outline Introduction to Digital Test Test as the quality problem Defect and fault models Hierarchical approach to test Decision Diagrams (beyond BDDs) Overview of tools developed at D&T Lab Conclusions

31. Technical University Tallinn, ESTONIA 31 Binary Decision Diagrams x1x1 x2x2 y x3x3 x4x4 x5x5 x6x6 x7x7 0 1 Simulation: 0 1 1 0 1 0 0 Boolean derivative and test generation: 1 0 Functional BDD

32. Technical University Tallinn, ESTONIA 32 Low-Level Test Generation on SSBDDs Test generation for a bridging fault: & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro D D D D D 1 1 1 1 x7x7 Network Defect WdWd 2. Activate a path: Bridge between leads 7 3 and 6: (dx 7,W d ) 6 7373 1 2 5 7272 7171 y 0 1 Path to 7 1 : x 1 = 1, x 2 = 1 Path from 7 1 : x 5 = 0 W d : x 6 = 0, x 7 = 1 1. Solve the constraint: Test pattern: 1 2 3 4 5 6 7 y 1 1 0 0 1 1

33. Technical University Tallinn, ESTONIA 33 Test Generation on High Level DDs y 4 y 3 y 1 R 1 +R 2 IN+ R 2 R 1 *R 2 IN*R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Multiple paths activation in a single DD Control function y 3 is tested Data path Decision Diagram High-level test generation with DDs: Conformity test Control: For D = 0,1,2,3: y 1 y 2 y 3 y 4 = 00D2 Data: Solution of R 1 + R 2  IN  R 1  R 1 * R 2 Test program:

34. Technical University Tallinn, ESTONIA 34 Hierarchical Test Generation on DDs Single path activation in a single DD Data function R 1 * R 2 is tested Data path Decision Diagram Hierarhical test generation with DDs: Scanning test Control: y 1 y 2 y 3 y 4 = x032 Data: For all specified pairs of (R 1, R 2 ) Test program: Low level test data

35. Technical University Tallinn, ESTONIA 35 High Level Fault Models K: ( If T,C) R D  F(R S1, R S2, … R Sm ),  N RTL statement: K- label T- timing condition C- logical condition R D - destination register R S - source register F- operation (microoperation)  - data transfer  N- jump to the next statement Components (variables) of the statement: RT level faults: K  K’- label faults T  T’- timing faults C  C’- logical condition faults R D  R D - register decoding faults R S  R S - data storage faults F  F’- operation decoding faults  - data transfer faults  N - control faults (F)  (F)’ - data manipulation faults

36. Technical University Tallinn, ESTONIA 36 Fault Modeling on High Level DDs High-level DDs (RT-level): Terminal nodes: RTL-statement faults: data storage, data transfer, data manipulation faults Nonterminal nodes: RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding, control faults

37. Technical University Tallinn, ESTONIA 37 DECIDER: Hierarchical ATPG R 2 M 3 e + M 1 a * M 2 b   R 1 IN    c d y 1 y 2 y 3 y 4 y 4 y 3 y 1 R 1 +R 2 + R 2 R 1 *R 2 IN*R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Modules or subcircuits are represented as word-level DD structures Logic Synthesis Scripts Design Compiler (Synopsys Inc.) Gate Level Descriptions SSBDD Synthesis SSBDD Models of FUs Hierarchical ATPG RTL Model (VHDL) FU Library (VHDL) FU Library (DDs) RTL DD Synthesis Test patterns RTL DD Model

38. Technical University Tallinn, ESTONIA 38 ATPG: Experimental Results Reference ATPGs: HITEC - T.M. Nierman, J.H. Patel, EDAC, 1991 GATEST - E.M.Rudnick et al., DAC, 1994 TTU: DET/RAND - hierarchical deterministic- random ATPG GENETIC - gate-level ATPG based on genetic algorithms

39. Technical University Tallinn, ESTONIA 39 TURBO-TESTER: Low-Level TPG Tools Test Generation BIST Simulation Methods: Deterministic Random Genetic Methods: BILBO CSTP Store/Generate Design Test Levels: Gate Macro Fault Simulation Methods: Single fault Parallel Deductive Fault Table Fault models: Stuck-at-faults Stuck-opens Delay faults Test Optimization Fault Diagnosis Fault Location

40. Technical University Tallinn, ESTONIA 40 Conclusions Traditional low-level test generation and fault simulation methods and tools for digital systems have lost their importance because of the complexity reasons As a promising compromise and solution is: to combine hierarchical approach with defect orientation Still three problems remain open: –defects in the interconnection network cannot be preanalyzed and described in the component libraries –combining the low-level solutions with high-level solutions in the hierarchical approach is often not possible because of the inconsistencies of signals –design for testability to enable the hierarchical approach is not always accepted because of the area overhead and performance restrictions BIST provides an alternative to the functional testing on hierarchical principles

41. Technical University Tallinn, ESTONIA 41 Conclusions of our Research Experience Who is a test engineer ? The test engineer is the man who is able to program a broken computer