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Short Cuts for Multiply and Divide For Positive Numbers 1. Multiply by 2 k is the same as shift k to the left, 0 fill 2. Divide by 2 k is the same as shift k to the right, 0 fill
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Short Cuts for Multiply and Divide For Positive Numbers 1. Multiply by 2 k is the same as shift k to the left, 0 fill 2. Divide by 2 k is the same as shift k to the right, 0 fill For 2’s Complement Numbers It does not always work!
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Short Cuts for Multiply and Divide For Positive Numbers 1. Multiply by 2 k is the same as shift k to the left, 0 fill 2. Divide by 2 k is the same as shift k to the right, 0 fill For 2’s Complement Numbers It does not always work! Ex: -5 = -0101, 2’s Complement = 1011 Divide by 4 by shift right 2, fill with ?
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Short Cuts for Multiply and Divide For Positive Numbers 1. Multiply by 2 k is the same as shift k to the left, 0 fill 2. Divide by 2 k is the same as shift k to the right, 0 fill For 2’s Complement Numbers It does not always work! Ex: -5 = -0101, 2’s Complement = 1011 Divide by 4 by shift right 2, fill with ? 1110 is 0001+1=0010 = 2 WRONG!
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Floating Point Numbers Normalized Mantissa or Significand and Exponent Add 0.713 x 10 -2 and 0.964 x 10 -1
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Floating Point Numbers Normalized Mantissa or Significand and Exponent Add 0.713 x 10 -2 and 0.964 x 10 -1 1.Align the exponents by shifting the smaller 0.0713 x 10 -1 0.9640 x 10 -1
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Floating Point Numbers Normalized Mantissa or Significand and Exponent Add 0.713 x 10 -2 and 0.964 x 10 -1 1.Align the exponents by shifting the smaller 0.0713 x 10 -1 0.9640 x 10 -1 2. Add 1.0353 x 10 -1
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Floating Point Numbers Add 0.713 x 10 -2 and 0.964 x 10 -1 1.Align the exponents by shifting the smaller 0.0713 x 10 -1 0.9640 x 10 -1 2. Add 1.0353 x 10 -1 3. Normalize0.10353 x 10 0
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Floating Point Numbers Add 0.713 x 10 -2 and 0.964 x 10 -1 1.Align the exponents by shifting the smaller 0.0713 x 10 -1 0.9640 x 10 -1 2. Add 1.0353 x 10 -1 3. Normalize0.10353 x 10 0 4. Round off 0.104 x 10 0
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Normalized REAL Binary Number: ± 1.yyyyyyyyy x 2 eeee
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Normalized REAL Binary Number: ± 1.yyyyyyyyy x 2 eeee Leading 1 Binary Point Significand = 1.yyyyyyyyy Exponent(signed) Arithmetic
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Normalized REAL Binary Number: ± 1.yyyyyyyyy x 2 eeee Leading 1 Binary Point Significand = 1.yyyyyyyyy Exponent(signed) Arithmetic
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Floating Point Numbers Add 1.0101 x 2 3 and 1.1011 x 2 1
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Floating Point Numbers Add 1.0101 x 2 3 and 1.1011 x 2 1 1.Align the exponents by shifting the smaller 1.0101 x 2 3 0.011011 x 2 3
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Floating Point Numbers Add 1.0101 x 2 3 and 1.1011 x 2 1 1.Align the exponents by shifting the smaller 1.0101 x 2 3 0.011011 x 2 3 2. Add 1.101111 x 2 3
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Floating Point Numbers Add 1.0101 x 2 3 and 1.1011 x 2 1 1.Align the exponents by shifting the smaller 1.0101 x 2 3 0.011011 x 2 3 2. Add 1.101111 x 2 3 3. Normalize – Check for Overflow and Underflow 1.101111 x 2 3
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Round - Off 4.563 significant digits +.0357 4.5957
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Round - Off 4.563 significant digits +.0357 4.5957 4.60 Rounded Off
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Round - Off 4.563 significant digits +.0357 4.5957 4.60 Rounded Off What if 4.5950 ?
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Round - Off 4.563 significant digits +.0357 4.5957 4.60 Rounded Off What if 4.5950 ? 4.60 Round to even
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Round - Off BinaryDecimal.00.01.25.10.50.11.75
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Round - Off BinaryDecimal.00.01.25.10.50 Are there any trailing 1’s ? If not, round to even.11.75
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Floating Point Numbers Add 1.0101 x 2 3 and 1.1011 x 2 1 1.Align the exponents by shifting the smaller 1.0101 x 2 3 0.011011 x 2 3 2. Add 1.101111 x 2 3 3. Normalize – Check for Overflow and Underflow 1.101111 x 2 3 4. Round to 4 bits Guard bit = 1 and Round bit = 1
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Floating Point Numbers Add 1.0101 x 2 3 and 1.1011 x 2 1 1.Align the exponents by shifting the smaller 1.0101 x 2 3 0.011011 x 2 3 2. Add 1.101111 x 2 3 3. Normalize – Check for Overflow and Underflow 1.101111 x 2 3 4. Round to 4 bits Guard bit = 1 and Round bit = 1 1.1100 x 2 3
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IEEE 754 Floating Point Standard Normalized REAL Binary Number: ± 1.yyyyyyyyy x 2 eeee IEEE 754 (-1) S x ( 1 + F) x 2 E-127 s exponent+127 significand - 1 1 bit E (8 bits) F (23 bits)
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IEEE 754 Floating Point Standard Normalized REAL Binary Number: ± 1.yyyyyyyyy x 2 eeee IEEE 754 (-1) S x ( 1 + F) x 2 E-127 s exponent+127 significand - 1 1 bit E (8 bits) F (23 bits) Bias Exponent E>0
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IEEE 754 Floating Point Standard Normalized REAL Binary Number: ± 1.yyyyyyyyy x 2 eeee IEEE 754 (-1) S x ( 1 + F) x 2 E-127 s exponent+127 significand - 1 1 bit E (8 bits) F (23 bits) Only Zero is F = 0 and E = 0 Simplifies data exchange Compare using integer processes Accuracy and round-off & Overflow and Underflow
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IEEE 754 Floating Point Standard 1 10000010 01010000000000000000000 =.25+.0625 =.3125
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IEEE 754 Floating Point Standard 1 10000010 01010000000000000000000 =.25+.0625 =.3125 E = 2 7 + 2 = 128 + 2 = 130
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IEEE 754 Floating Point Standard 1 10000010 01010000000000000000000 =.25+.0625 =.3125 E = 2 7 + 2 = 128 + 2 = 130 Number = (-1) S x ( 1 + F) x 2 E-127
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IEEE 754 Floating Point Standard 1 10000010 01010000000000000000000 =.25+.0625 =.3125 E = 2 7 + 2 = 128 + 2 = 130 Number = (-1) S x ( 1 + F) x 2 E-127 = – ( 1 +.3125) x 2 130 – 127
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IEEE 754 Floating Point Standard 1 10000010 01010000000000000000000 =.25+.0625 =.3125 E = 2 7 + 2 = 128 + 2 = 130 Number = (-1) S x ( 1 + F) x 2 E-127 = – ( 1 +.3125) x 2 130 – 127 = – 1.3125 x 2 3 = – 1.3125 x 8 = – 10.5
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IEEE 754 Floating Point Standard Consider representing –5 in IEEE 754 Floating Point Format
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IEEE 754 Floating Point Standard Consider representing –5 in IEEE 754 Floating Point Format 5 = 101.0 x 2 0 = 1.01 x 2 2
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IEEE 754 Floating Point Standard Consider representing –5 in IEEE 754 Floating Point Format 5 = 101.0 x 2 0 = 1.01 x 2 2 IEEE 754 (-1) S x ( 1 + F) x 2 E-127 s exponent+127 significand - 1 1bit E (8 bits) F (23 bits)
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IEEE 754 Floating Point Standard Consider representing –5 in IEEE 754 Floating Point Format 5 = 101.0 x 2 0 = 1.01 x 2 2 IEEE 754 (-1) S x ( 1 + F) x 2 E-127 s exponent+127 significand - 1 1bit E (8 bits) F (23 bits) E –127 = 2 E = 2 + 127 = 129 = 1000 0001
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IEEE 754 Floating Point Standard Consider representing –5 in IEEE 754 Floating Point Format 5 = 101.0 x 2 0 = 1.01 x 2 2 IEEE 754 (-1) S x ( 1 + F) x 2 E-127 s exponent+127 significand - 1 1bit E (8 bits) F (23 bits) E –127 = 2 E = 2 + 127 = 129 = 1000 0001 1 +F = 1.01000...
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IEEE 754 Floating Point Standard Consider representing –5 in IEEE 754 Floating Point Format 5 = 101.0 x 2 0 = 1.01 x 2 2 IEEE 754 (-1) S x ( 1 + F) x 2 E-127 s exponent+127 significand - 1 1bit E (8 bits) F (23 bits) 1 1000 0001 0100 0000.... 0000 E = 2 + 127 = 129 = 1000 0001 1 +F = 1.01000...
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IEEE 754 Floating Point Standard Normalized REAL Binary Number: ± 1.yyyyyyyyy x 2 eeee Double Precision IEEE 754 (-1) S x ( 1 + F) x 2 E-1023 s exponent+1023 significand - 1 1 bit E (11 bits) F (20 bits) significand – 1 (continued) F (32 bits)
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Sequential Network Structures - Review X1 X2 Xn Y1 Y2 Ym Q1 Q2 Qm Z1 Z2 Zk Combinational Logic Register Q Clock Stability Condition clk i Y Q Input Output
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Flip - Flop with NOR Gates Q = R+Q Q = S+Q R S Present State RS Q 00 01 10 11 0 1 Next State Q
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Flip - Flop with NOR Gates Q = R+Q Q = S+Q R S Present State RS Q 00 01 10 11 0 0 1 1 Next State Q
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Flip - Flop with NOR Gates Q = R+Q Q = S+Q R S Present State RS Q 00 01 10 11 0 0 1 1 1 1 Next State Q
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Flip - Flop with NOR Gates Q = R+Q Q = S+Q R S Present State RS Q 00 01 10 11 0 0 1 0 1 1 1 0 Next State Q
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Flip - Flop with NOR Gates Q = R+Q Q = S+Q R S Present State RS Q 00 01 10 11 0 0 1 0 ? 1 1 1 0 ? Next State Q
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D-latch C D Q D C Q Q S R
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C D Q D C Q Q S R
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D flip-flop Output changes only on the trailing clock edge QQ _ Q D latch D C D latch D C D C Q D C Q
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D flip-flop Output changes only on the trailing clock edge QQ _ Q D latch D C D latch D C D C Q D C Q
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Sequential Network Structures - Review X1 X2 Xn Y1 Y2 Ym Q1 Q2 Qm Z1 Z2 Zk Combinational Logic Register Q Clock Stability Condition clk i Y Q Input Output
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Five Components of Computers Input Output Memory Control Datapath Processor
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Start by Building the Datapath 1.Access the Instruction from Memory 2.Access the Data from Registers 3.Perform the Instruction 4.Write the Result
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PC Instruction Memory Next PC Logic Instruction Address Simplified Overview Access the Instruction from Memory
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PC Instruction Memory Next PC Logic Instruction Address Register File Simplified Overview Access the Data from Registers
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PC Instruction Memory Next PC Logic Instruction Address Register File ALU Simplified Overview Perform the Instruction
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PC Instruction Memory Next PC Logic Instruction Address Register File ALU Data Memory Addr Data In Data Out Simplified Overview Write the Result
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PC Instruction Memory Next PC Logic Instruction Address Register File ALU Data Memory Addr Data In Data Out Simplified Overview Timing Assumption
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