1. In-Place Decomposition for Robustness in FPGA Ju-Yueh Lee, Zhe Feng, and Lei He Electrical Engineering Dept., UCLA Presented by Ju-Yueh Lee Address comments to Lei He (lhe@ee.ucla.edu)

2. Outline Preliminaries and Motivations In-Place Decomposition(IPD) Formulations IPD Properties and Algorithms Experimental Results Conclusions and Future Work

3. Single Event Upset (SEU) Soft errors caused by single event upsets (SEUs) due to cosmic rays, supply voltage fluctuations, electromagnetic coupling  Result in bit flips in the affected memory elements SRAM-based FPGA  High density  Reprogrammability  Susceptible to SEU  Configuration memory and user FF and register  Soft errors in configuration memory have permanent impact until scrubbing

4. Related Work Explicit redundancy  “Triple Modular Redundancy (TMR)” Logic masking with little or no area overhead  “Robust FPGA resynthesis based on fault tolerant boolean matching”, [Hu-et al, iccad08]  “IPR: In-place reconfiguration for FPGA fault tolerance”, [Feng-et al, iccad09]

5. Related Work “Fault-tolerant Resynthesis with Dual-Output LUT”, [Lee-et al, aspdac2010] Original LUT Duplication and Encoding

6. Limitation: Slow Design Closure Logic coding in fanout LUT leads to Extra interconnects  more delay, more routing congestion, and more interconnect faults Slow design closure between logic and physical syntheses Extra interconnects

7. Limitation: not Applicable to Large Functions Duplication cannot be applied to  6-input functions for Virtex-5 with LUT6  5- and 6-input functions for Stratix-IV with ALM

8. Outline Preliminaries and Motivation In-Place Decomposition(IPD) Formulations IPD Properties and Algorithms Experimental Results Conclusions and Future Work

9. Fault Metrics Criticality of a configuration SRAM bit Mean-Time-To-Failure (MTTF)  System level measurement of reliability  For single fault model, MTTF  1/average(Cb)

10. Logic Decomposition Decomposition : F = C( F1, F2, ……, Fn ) (C Is the logic function of the converging logic, e.g., AND)R) Original LUT Decomposed LUT Decomposition

11. Circuit Implementation of Decomposition Logic decompositon by decomposable LUT Converging logic by fanout programmable logic block (PLB) or carry chains/adders Carry chains/adders has only 10% to 50% utilization rate, an ideal choice for converging Altera Stratix-IVXilinx Virtex-5

12. Circuit Implementation of Decomposition Logic decompositon by decomposable LUT Converging logic by fanout programmable logic block (PLB) or carry chains/adders Carry chains/adders has only 10% to 50% utilization rate, an ideal choice for converging Altera Stratix-IVXilinx Virtex-5

13. In-Place Decomposition Converging in a same PLB  In-place decompositionor OR) Original LUT Decomposition Decomposable LUT Decomposable LUT Carry Chain or Adder Carry Chain or Adder

14. Carry Chain/Adder Configuration Configure Carry Chaings/Adders as AND/OR gates

15. Example 1 : In-Place Duplication An example of In-Place Duplication on “n24” node from “alu4” benchmark circuit In-Place Duplication IPD F : 0xA280 Avg. Crit. : 0.6876 F : 0xA280 Avg. Crit. : 0.6876 F1 : 0xA280 F2 : 0xA280 Avg. Crit. : 0.2116 F1 : 0xA280 F2 : 0xA280 Avg. Crit. : 0.2116 Original LUT

16. Example 2 : In-Place Decomposition IPD F : 0x8000 (duplication not applicable) Avg. Crit. : 0.8 F : 0x8000 (duplication not applicable) Avg. Crit. : 0.8 F1 : 0x7 F2 : 0x7 Avg. Crit. : 0.4 F1 : 0x7 F2 : 0x7 Avg. Crit. : 0.4 In-Place Decomposition Original LUT

17. Recap of IPD Given a placed and routed circuit Objective decompose LUTs to minimize criticalities IPD Advantages :  No PLB level overhead  Fast design closure  Can be applied to large functions

18. Outline Preliminaries and Motivation In-Place Decomposition(IPD) Formulations IPD Properties and Algorithms Experimental Results Conclusions and Future Work

19. IPD Property 1 An optimal LUT decomposition can be obtained by duplication when duplication is applicable

20. IPD Property 1 An optimal LUT decomposition can be obtained by duplication when duplication is applicable

21. In-place Duplication vs Decomposition In-Place Duplication In-Place Decomposition

22. IPD Property 2 An optimal LUT decomposition can be obtained by applying AND or OR converging logic

23. IPD Property 2 An optimal LUT decomposition can be obtained by applying AND or OR converging logic

24. IPD Algorithm Objective : - Minimize LUT criticality Subject to : - Circuit function is preserved - LUT architecture constraints - Logic masking constraints IPD problem is formulated to an integer linear programming (ILP) problem and solved optimally for each PLB

25. Boolean Matching Constraints The circuit function is preserved by boolean matching constraints considering LUT architecture  Boolean matching for each input pattern  Each SRAM bit is matched such that the LUT function is preserved

26. Logic Masking Constraints The criticality reduction is constrained by the logic masking that IPD can produce  Criticality update constraint

27. Logic Masking Constraints The criticality reduction is constrained by the logic masking that IPD can produce  Criticality update constraint

28. Outline Preliminaries and Motivation In-Place Decomposition(IPD) Formulations IPD Properties and Algorithms Experimental Results Conclusions and Future Work

29. Experimental Settings Assume single fault Apply to architectures similar to Xilinx Virtex-5 and Altera Stratix-IV FPGAs Using the 10 largest MCNC combinational circuits mapped to 6-input LUT by ABC technology mapper

30. Experiment on Virtex-5 Similar Architecture 2.43X MTTF improvement on ex1010 circuit under 0% carry chain utilization rate 5-input or smaller functions are in-place duplicated  6-input functions are hardly improved

31. Experiment on Stratix-IV Similar Architecture 9.67X MTTF improvement on apex2 circuit under 0% adder utilization rate 4-input or smaller functions are in-place duplicated  5 & 6-input functions are decomposed with four inputs shared

32. IPD Improvement Indicator A good IPD improvement indicator by the criticality difference between on set and off set of SRAM bits

33. Outline Preliminaries and Motivation In-Place Decomposition(IPD) Formulations IPD Properties and Algorithms Experimental Results Conclusions and Future Work

34. Proposed a new robust technique leveraging decomposable LUTs and built-in carry chain/adder in modern FPGAs  1.59X MTTF improvement for architecture similar to Xilinx Virtex-5  4.51X MTTF improvement for architecture similar to Altera Stratix-4 Future works  Develop a more accurate robustness analysis and a more efficient algorithm for sequential circuits  Study the interaction between IPD and existing fault tolerant techniques for robustness optimization.

35. Thanks In-place Decomposition for Robustness in FPGA Ju-Yueh Lee, Zhe Feng, and Lei He

36. IPD Experimental Results (1) IPD on 10 biggest MCNC combinational circuits

37. IPD Experimental Results (1) IPD on 10 biggest MCNC combinational circuits 9.67X improvement

38. IPD Algorithm Flow

39. Dual-Output LUT Configurations Xilinx Virtex-5 6-input LUT : Altera Stratix-IV ALM : Func. sizes# of shared inputs 5, 55 Func. sizes# of shared inputs 4, 40 5, 30 5, 41 5, 52 6, 64

40. IPD Experimental Results IPD under different carry chain/adder utilization rate 9.67X MTTF improvement on apex2 circuit

41. InputOutputCrit. 0000.2 0110.2 1000.4 1110.2 InputOutputCrit. 0000.2 0110.2 1000.4 1110.2 Criticality Update for In-Place Duplication (1) InputOutputCrit. 0000.2 0110.2 1000.4 1110.2 Duplication Average Crit. = 0.125 Average Crit. = 0.25 InputOutputCrit. 00not used0 01not used0 10not used0 11not used0

42. Criticality Update for In-Place Duplication (2) AND Encoding Average Crit. = 0.08 InputOutputCrit. 0000.2 0110.2 1000.4 1110.2 InputOutputCrit. 0000.2 0110.2 1000.4 1110.2 Average Crit. = 0.25 InputOutputCrit. 0000 0110.2 1000 1110.2 InputOutputCrit. 0000 0110.2 1000 1110.2

43. InputOutputCrit. 0000.1 0100.05 1000.1 1110.05 InputOutputCrit. 0000.1 0100.1 1000.05 1110.05 Criticality Update for In-Place Decomposition Duplication Average Crit. = 0.125 Average Crit. = 0.075 InputOutputCrit. 00000.05 00100.05 01000.05 01100.05 10000.05 10100.05 11000.05 11110.65