1. Evaluation of novel n + -in-p pixel and strip sensors for very high radiation environment Y. Unno a, S. Mitsui a, R. Hori a, R. Nagai g, O. Jinnouchi g, Y. Takahashi h, K. Hara h, S. Kamada b, K. Yamamura b, A. Ishida b, M. Ishihara b, T. Inuzuka b, Y. Ikegami a, Y. Takubo a, S. Terada a, J. Tojo a, R. Takashima c, I. Nakano d, K. Hanagaki e, N. Kimura i, K. Yorita i a High Energy Accelerator Research Organization (KEK) and The Graduate University for Advanced Studies (SOKENDAI) b Hamamatsu Photonics K.K. c Department of Education, Kyoto University of Education d Department of Physics, Okayama Univeristy e Department of Physics, Osaka University g Department of Physics, Tokyo Institute of Technology h Institute of Pure and Applied Sciences, Univeristy of Tsukuba i Research Institute for Science and Engineering, Waseda University Y.Unno, PIXEL2012 at Inawashiro, 2012/9/61

2. n + -in-p Benefits and Issues Starting with “p-type” silicon, with n + - readout, (n-in-p), has benefits: – Tolerance against radiation (bulk) damage Depletion from the readout side always Good signal even partially depleted, initially or heavily damaged towards the end of life – Collecting faster carrier, electrons Larger signal, reduced charge trapping – Single-sided process Cheaper than double-side process More foundries and available capacity, world-wide – Easier handling/testing due to more robust back-side than patterned – Wafer availability in 6-in. with higher resistivity Specific requirements – N-side Isolation against electron-layer in the silicon surface attracted to the “positive” charges in the Si-SiO 2 interface p-stop or p-spray – Bias structure if AC-coupling readout, e.g., strip sensors if requesting testability in DC-coupling, e.g., pixel sensors – HV protection between the front edge and the ASIC, in hybrid pixel modules Y.Unno, PIXEL2012 at Inawashiro, 2012/9/62 n+n+ p - bulk Al Bias Ring p-spray or p-stop p+p+ Guard Ring e-e- Un-depleted Edge Ring SiO 2

3. Axial Stereo Novel n + -in-p Strip Sensors Collaboration of ATLAS with Hamamatsu Photonics K.K. (HPK) Silicon wafers – 6 in., p-type, FZ, 320 µm thick wafers – >3 kΩ cm wafers available industrially Strip sensors – large area 9.75x9.75 cm 2 sensors – 4 segments 2 axial, 2 stereo 1280 strip each, 74.5 mm pitch – Miniature sensors 1x1 cm 2 for irradiation studies – Y. Unno, et. al., Nucl. Inst. Meth. A636 (2011) S24-S30 – And the poster (ID=8) Y.Unno, PIXEL2012 at Inawashiro, 2012/9/63

4. Novel n + -in-p Pixel Sensors n-in-p 6-in. wafer process in HPK – ATLAS FE-I3 and FE-I4 pixel sensors – Isolation structures p-stop (common, individual) or p-spray – Biasing structures Punth-thru dot at 4-corner (PTLA) or PolySi resister “Bias rail” is a metal over insulator, no implant underneath. No electrode in the silicon, other than the bias “dot” – Y. Unno et al., Nucl. Instr. Meth. A650 (2011) 129–135 Thinned sensors – Finishing 320 µm wafer process first – Thinning the wafers to 150 µm Y.Unno, PIXEL2012 at Inawashiro, 2012/9/64 PTLA PolySi Bias rail Biasing Scheme Isolation scheme (a) (b)(c) (d)(e)(f) HPK n-in-p 6-in. wafer FE-I4 2-chip pixels FE-I4 1-chip pixels FE-I3 1-chip pixels FE-I3 4-chip pixels FE-I3 (~1cm □ ) FE-I4 (~2cm □ ) FE-I4 pseudo 4-chip pixels

5. Pixel modules - Bumpbonding Latest achievement – Lead-free bumps (SnAg) – 4 cm x 4 cm pixel sensor – 4x FE-I4 (2 cm x 2 cm) readout ASIC’s – 80 col.*336 row*4 chips =1M bumps – A sample in the HPK display table Y.Unno, PIXEL2012 at Inawashiro, 2012/9/65 ASIC side Sensor side

6. The goals of R&D Application – For the very high radiation environment, e.g., – High-Luminosity LHC which aims to collect data of 3,000 fb -1 Presently running LHC goal is 300 fb -1 Fluences of hadronic particles in HL-LHC – Pixels: ~2x10 16 1-MeV neutron-equivalent (neq)/cm 2 – Strips: ~1x10 15 neq/cm 2 Understanding of the radiation effect, specially in the surface, after the studies of irradiated sample: – Surface resistance – Interstrip resistance – Punch-thru onset voltage – PTP structures – Effect of the surface potential – Bias rail, Bias-PTP gate – Potential of the p-stop Y.Unno, PIXEL2012 at Inawashiro, 2012/9/66

7. Interstrip Resistance Interstrip resistance – decreases with fluence – increases with bias voltage Y.Unno, PIXEL2012 at Inawashiro, 2012/9/67 Non-irrad. 5x10 12 neq/cm 2 1x10 13 1x10 14 1x10 15

8. No gate PTP Onset Voltage – after irradiation Onset voltage – Increases with fluence Y.Unno, PIXEL2012 at Inawashiro, 2012/9/68 Full gate Non-irradiated 1x10 13 5x10 12 1x10 14 1x10 15 Strip Bias rail Full gate - Irradiated 10 kΩ 100 kΩ 1 MΩ ~5 mA PTP - Insurance for protecting integrated AC coupling capacitors from beam splash ∆V (Implant-Metal) ≤100 V http://dx.doi.org/10.1016/j.nima.2012.05.071

9. Bias Rail Effect – after irradiation Beamtests with MIP particles Thin (150 µm) FE-I4 pixel sensors Irradiation (2x10 15 neq/cm 2 ) – Successful operation up to 1000 V Reduction of efficiency specially underneath the bias rail Y.Unno, PIXEL2012 at Inawashiro, 2012/9/69 99.8% 95.7% 95.0% (a) PolySi x p-stop(b) PolySi x p-stop, 2x10 15 (c) PTLA x p-stop Bias rail No bias rail http://dx.doi.org/10.1016/j.nima.2012.04.081

10. Insensitive area - after Irradiation Underneath the gate (metal) seems insensitive after irradiation – 20 µm width Y.Unno, PIXEL2012 at Inawashiro, 2012/9/610 Y. Unno et al., IEEE TNS 44 (1997) 736-742 1016.9 +/- 9.5 µm 992.5 +/- 5.6 µm Irradiated: 1x10 15 n eq /cm 2 Non-irradiated 995 µm 1015 µm New result from a beamtest (Poster ID=52)

11. Sensor Edge – Field Width Field width – Area with no implantation Required field width – decreases as fluence increased Hot electron images confirm that – the highest electric field is – in the bias ring (n + implant) – not in the edge ring (p + implant) Y.Unno, PIXEL2012 at Inawashiro, 2012/9/611 http://dx.doi.org/10.1016/j.nima.2012.05.071 1x10 14 neq/cm 2 10uA at 2000 V -15 °C

12. n+n+ p - bulk Al Bias Ring p-spray or p-stop p+p+ Guard Ring e-e- Un-depleted Edge Ring SiO 2 Potential of p-stop Wider the pitch, larger the potential Potential decreases and saturates as fluence increase Y.Unno, PIXEL2012 at Inawashiro, 2012/9/612

13. P-stop Potential - TCAD TCAD model – Thickness 150 µm, Bias voltage = 200 V – Radiation damage in bulk - Bulk resistivity is reduced by increasing the acceptor states, N eff ~ 1.4 x 10 12 /cm 3, full depletion voltage of ~1 kV at 320 µm. Y.Unno, PIXEL2012 at Inawashiro, 2012/9/613 I/F +1e11/cm 2 I/F -1e11/cm 2 I/F +1e12/cm 2

14. P-stop Potential - TCAD Negative charge-up – does not explain “p-stop potential”. – explains “PTP onset voltage”, hot spots at the bias ring. Positive charge-up – explains “decrease of p-stop potential”, but – does not explain “PTP onset voltage increase” nor the highest field at the bias ring side. Y.Unno, PIXEL2012 at Inawashiro, 2012/9/614 I/F charge +1e11/cm 2 I/F charge -1e11/cm 2 I/F charge +1e12/cm 2

15. Interface charges Fixed oxide charge (Q t ) – known to be “+” Interface trapped charge (Q it ) – can be “+” or “-” – depending on the conditions Y.Unno, PIXEL2012 at Inawashiro, 2012/9/615

16. Our explanation, backed with TCAD After irradiation, – Primary factor is the increase of “+” charges, e.g., in the fixed oxide charge – The evidences suggest that there is a secondary factor of increase of “-” charges in the “interface trapped charge”. – This may explain all observations. An example of TCAD… Y.Unno, PIXEL2012 at Inawashiro, 2012/9/616 … failed to converge, though.

17. Summary Novel n + -in-p silicon strip and pixel sensors have been fabricated at HPK successfully. – and lead-free bumpbonding as well, which makes one-stop fabrication of pixel detectors from the sensor to the module. – Issues especially associated with the n + -in-p sensors were addressed. Isolation structures that are robust against the bias voltage up to 1000 V. We have accumulated a number of evidences on the surface damage, after irradiation, that we explain, backed by TCAD simulation, – (1) Primary factor is “+” charge-up of, e.g., Fixed oxide charge, and – (2) Secondary factor is “-” charge-up of “interface trapped charge”. Y.Unno, PIXEL2012 at Inawashiro, 2012/9/617

18. Backup slides Y.Unno, PIXEL2012 at Inawashiro, 2012/9/618

19. P-stop Potential - TCAD Silicon wafer – 320 µm, 3 kΩ cm (=4.7x10 12 cm -3 ) Condition: Non-irradiated Ratio of p-stop potential-to-bias voltage seems stable for the change of the bulk resistivity Y. Unno et al., Nucl. Instr. Meth. A636 (2011) S118–S124 200 V bias 75 µm ptich 19Y.Unno, PIXEL2012 at Inawashiro, 2012/9/6