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Wnopp 20001 Memory device Introduction n Memory Cell n Memory Word n Byte n Capacity n Address n Read Operation n Write Operation n Access Time n Volatile.

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Presentation on theme: "Wnopp 20001 Memory device Introduction n Memory Cell n Memory Word n Byte n Capacity n Address n Read Operation n Write Operation n Access Time n Volatile."— Presentation transcript:

1 wnopp 20001 Memory device Introduction n Memory Cell n Memory Word n Byte n Capacity n Address n Read Operation n Write Operation n Access Time n Volatile Memory n Random-Access Memory (RAM) n Sequential-Access Memory (SAM) n Read/Write Memory (RWM) n Read-Only Memory n Static Memory Device n Dynamic Memory Device n Internal Memory n Mass Memory

2 wnopp 20002 General Memory Operation n Select the address. n Select R/W operation. n Supply the input to be store (W operation). n Hold the output data comings from memory (R operation). n Enable (or Disable) the memory Example Memory chip 2K x 8. How many total bits can chip store? 2K = 1 x 1024 = 2048 words 1 word = 8 bits 2K x 8 = 2048 x 8 = 16384 bits Which memory store the most bits: 5M x 8, 1M x 16 5M x 8 = 5 x 1,048,576 x 8 = 4,1943,040 bits 1M x 16 = 1,048,576 x 16 = 1,677,7216 bits

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4 4 CPU- Memory connections Write operation 1. CPU ๐ Binary address on address bus. 2. CPU ๐ Data on data bus. 3. CPU ๐ control signal. 4. ICs decode address location. 5. Transfer data to the selected location. Read operation 1. CPU ๐ Binary address on address bus. 2. CPU ๐ control signal. 3. ICs decode address location. 4. Place data ๐ data bus ๐ Transfer data to CPU

5 wnopp 20005 Read-Only Memory

6 wnopp 20006 ROM architecture

7 wnopp 20007 ROM timing read operation PROMs fusible links

8 wnopp 20008 Structure of a bipolar MROM (Mask-Programmed )

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10 10 Example of a programmable logic device

11 wnopp 200011 PROM architecture for PLDs

12 wnopp 200012 PAL architecture

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14 wnopp 200014 Cell arangement in 16Kx1 DRAM Symbolic representation of DRAM Symbol & mode table for 6264 SRAM

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