1. Week 5
RISC &. CISC

2. CISC Complex Instruction Set Computer
Large number of complex instructions
Low level
Facilitate the extensive manipulation of low-level computational elements and events such as memory, binary arithmetic, and addressing.

3. CISC Examples Examples of CISC processors are the
System/360(excluding the 'scientific' Model 44),
VAX,
PDP-11,
Motorola family
Intel x86 architecture based processors.

4. Pro’s Emphasis on hardware Includes multi-clock complex instructions
Memory-to-memory: "LOAD" and "STORE" incorporated in instructions
Small code sizes, high cycles per second
Transistors used for storing complex instructions

5. Con’s
That is, the incorporation of older instruction sets into new generations of processors tended to force growing complexity.
Many specialized CISC instructions were not used frequently enough to justify their existence.
Because each CISC command must be translated by the processor into tens or even hundreds of lines of microcode, it tends to run slower than an equivalent series of simpler commands that do not require so much translation.

6. The CISC Approach
MULT 2:3, 5:2

7. RISC Reduced Instruction Set Computer Small number of instructions
instruction size constant
bans the indirect addressing mode
retains only those instructions that can be overlapped and made to execute in one machine cycle or less.

8. RISC Examples Apple iPods (custom ARM7TDMI SoC)
Apple iPhone (Samsung ARM1176JZF)
Palm and PocketPC PDAs and smartphones (Intel XScale family, Samsung SC ARM9)
Nintendo Game Boy Advance (ARM7)
Nintendo DS (ARM7, ARM9)
Sony Network Walkman (Sony in-house ARM based chip)
Some Nokia and Sony Ericsson mobile phones

9. Pro’s Emphasis on software Single-clock, reduced instruction only
Register to register: "LOAD" and "STORE" are independent instructions
Low cycles per second, large code sizes
Spends more transistors on memory registers

10. The RISC Approach
LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A

11. Performance

12. Performance
The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program.

13. Structure of Computer Systems

14. CISC v.s. RISC CISC – Complex Instruction Set Computer
RISC - Reduced Instruction Set Computer
Historical perspective:
at first computers had a limited instruction set because of technological limitations (number of switching elements was limited)
as integration technology improved:
more instructions were included in the set of a computer
more complex operations implemented in instructions => more complex instructions
consequences:
CPU became more and more complex
CPU became slower (relative to the clock frequency)
higher CPI and limited clock frequency

15. CISC Reasons for complex instruction set computers Benefits:
more powerful instructions
e.g. floating point arithmetic instructions
assembly language instructions closer to high level language instructions
e.g. loops, complex conditional jumps
more complex addressing modes, as support for complex data structures
addressing: indexed, based, mixed, scaled, etc.
Benefits:
easier programming in assembly language
less instructions needed to write an application
easier compilation of high level languages
support for complex data structures

16. CISC Statistical measurements (during the ’70s) Surprising results
which instruction types are more often used in different types of applications ?
does the programmers use the available complex instructions?
Surprising results
programmers prefer simple instructions
complex instructions are used just occasionally, for some very specific operations (e.g. sine, arc tang. log, exponential, etc.)
most of the time the processor is executing simple instructions from a limited set
Conclusion:
the speed limitation caused by a complex instruction set is not justified
let’s do things simpler and faster

17. RISC RISC = Reduced Instruction Set Computer
Principle: sacrifice everything for speed
reduce the number of instructions – make CPU simpler
get rid of complex instructions, which may slow down the CPU
use simple addressing modes – less time spent to compute the address of an operand
limit the number of accesses to the memory
if a given operation cannot be executed in one clock period than do not implement it in an instruction
extensive use of pipeline architecture – in order to reach CPI=1 (one instruction per clock period)

18. RISC - Main features
limited number of instructions in the instruction set:
30-40 instructions v.s in case of CISC
no complex instructions
every instruction executes only one operation
instructions have fixed format
fixed length
few combinations of fields inside the instruction code
instructions executed in one clock period (except Load and Store instructions)
through intensive use of pipeline architecture
every instruction have the same number of pipeline stages

19. RISC - Main features Increased set of general purpose registers
e.g registers
instructions operating with registers are executed in the shortest time
compensate the lack of instructions operating with the memory
Use of multiple register sets
fast and easy context switch
use of register set windows

20. RISC - Main features
Only two instructions operate (have access) to the memory locations:
Load – read data from the memory into a register
Store – write the data from a register into the memory
Load and Store instructions require two accesses to the memory:
one to read the instruction code
one to read or write the data
Load and store instructions are the only instructions which are executed in two clock periods
all the other instructions from the set are operating with registers or a register and a constant

21. RISC - Main features Hard to write applications in assembly language
lack of more powerful instructions and addressing modes
A program on a RISC is more optimized than the same program written on a CISC
only those operations are used which are strictly necessary
More effort for programming, less time in execution
it is worth to have a greater time spent on programming if at the end the program will be executed many times in a shorter time !?

22. RISC - Main features
The CPU implemented in pure hardware (no microprogramming)
instructions are decoded and executed using hardware components
higher speed less execution steps
Compilers are more difficult to implement

23. RISC v.s. CISC Parameter RISC CISC Instruction types Simple Complex
Number of instructions
Reduced (30-40)
Extended ( )
Duration of an instruction
One cycle
More cycles (4-120)
Instruction format
Fixed
Variable
Instruction execution
In parallel (pipeline)
Sequential
Addressing modes
Instructions accessing the memory
Two: Load and Store
Almost all from the set
Register set
multiple
unique
Complexity
In compiler
In CPU (micro-program)

24. Performance of RISC v.s. CISC
CISC: less long
execution time = no_instructions*CPI*Tclk
RISC: more short
Hard to tell which is the best
A combination of CISC and RISC may be the solution:
RISC inside, CISC outside – see Pentium processors
complex instructions translated into simple (RISC) instructions

25. Examples of RISC architectures
Academic implementations:
RISC I si II – Berkley University (prof. Patterson, 1980)
MIPS – Univ. Stanford (prof. Hennessy, 1982)
First commercial implementations
IBM 801 – companis IBM (1975)
ALPHA – companis DEC
SPARC – Sun Microsystems (1987)
General purpose processors:
PowerPC – IBM is Motorola
ARM architecture

26. Applications of RISC architectures
Powerful Workstations
used for engineering purposes (ex. Sun station)
High-end graphical stations
used for simulation, animation, etc.
Microcontrollers
used for control applications and peripheral devices
Digital signal processors
used for signal processing
Mobile devices
iPAD, tablet, support for Android systems

27. RISC architecture examples MIPS
Microprocessor without Interlocking Pipe Stages or
Million Instruction per Second processor:
developed by Prof. Hennessy at Stanford University (1982)
a classical pipeline architecture used as reference for teaching basic concepts about computers
features:
32 internal registers
reduced instruction set
instructions with fixed length (4 bytes); types: R,J, I
3 operands instructions (source, destination, target)
(see a previous course for details)

28. RISC architecture examples Microcontrollers
all components of a micro-computer system in a single integrated circuit:
CPU
program memory
data memory
parallel I/O ports
serial ports
timers, counters
converters: ADC, DAC, PWM
watchdog
used for control applications:
monitoring
feedback control

29. RISC architecture examples Microcontrollers
Example PIC16Fxx
CPU – simple, RISC architecture
Instruction format – fixed, 14 bits/instruction
only 35 instructions
data format: 8 bits
Internal memory – inside the chip - Harvard architecture – data separated from instructions
data memory – 368 bytes SRAM, organized on banks
instruction memory – 8kinstructions
256 bytes EEPROM (non-volatile memory)
Interfaces:
serial UART and SPI
Convertors: 10 bits ADC with 8 channel multiplexer
3 timers
parallel ports
ICD – In Circuit debug functionality
Package: 28,40 or 44 pins
Data memory
Bank 0 Bank 1 2, 3
1Fh
Ports area
General registers
User data area

30. RISC architecture examples PowerPC
PowerPC = Performance Optimization With Enhanced RISC – Performance Computing
designed as a competitor for the Intel X86 processor family
developed by Apple, IBM and Motorola (1991) as an open architecture
extension of the IBM’s Power architecture
RISC and superscalar architecture
initially intended for PCs, now used for embedded and high performance computers
32 and 64 bit processors
many versions: PowerPC 601, 602, 604, 620,740, 74000
computers made with PowerPC:
Macintosh, Apple
RS6000, (RISC System 6000), IBM
embedded computers