1. CSE 171 Lab 11
Digital Voltmeter

2. Objective: a Xilinx XC95108 PC84 CPLD chip
a PLDT-3 Trainer Board with a 4 MHz clock
an ADC0831 Analog-to Digital Converter chip

3. Background VIN ADC Output = 255 * , so set VREF = 5.0 V. VREF
Then, if VIN = 5.0 V, the ADC Output = 255, and as
2 * 255 = 510, the ADC Output * 2 = 102 * VIN
250
If we set VIN = * test voltage (VT) , or VT * 0.980,
255
then the ADC Output * 2  100 * VT

4. Use of a voltage divider to approximate VT * 0.980
IT =
(R1 + R2)
Test
Voltage
Input (VT)
R1 = 4.7 K
R2 = 220 K
VIN IT
VIN = IT * R2 R2
= VT *
(R1 + R2)
220 K
= VT *
224.7 K
 VT *

5. Analog-to-Digital Converter Circuit
Converter ADC0831
VCC
CLK DO
VREF
VIN (+)
VIN (-)
GND CS
Voltage
Input
+5 VDC
Xilinx
XC95108
Interface
4.7 K
220 K 1 2 4 3 8 7 5 6

6. The max. clock speed of the ADC0831 chip is 400 Khz, so we need a 4-bit counter to divide the PLDT-3 board
4 MHz clock frequency by 16.
Clock
4.0 MHz Q0
2.0 MHz Q1
1.0 MHz Q2
0.5 MHz Q3
0.25 MHz
By extending this counter to eight bits, additional Analog-to-Digital Converter control signals can be generated.

7. Analog-to-Digital Converter Circuit
Converter ADC0831
VCC
CLK DO
VREF
VIN (+)
VIN (-)
GND CS
Voltage
Input
+5 VDC
Xilinx
XC95108
Interface
4.7 K
220 K 1 2 4 3 8 7 5 6

8. Q3 Q4 Q5 Q6 Q7
Q3 (CLK)
Q6 & Q7 (CS)
Data Out (DO)

10. Xilinx XC95108
PC84 CPLD
Clock Divider
Counter Q7..Q0
4 MHz Clock
ADC0831
Interface Q3
CLK Q7 Q6 CS DO

11. Q3 Q4 Q5 Q6 Q7 Q3 (CLK) Q6 & Q7 (CS) Data Out (DO) !Q3 shift (S)
!Q3 shift (S)
[Q7..Q4] == 10
(Capture)
!Q3 display (D)

12. Xilinx XC95108
PC84 CPLD
Clock Divider
Counter Q7..Q0
4 MHz Clock Q3 Q7 Q6
CLK CS DO
ADC0831
Interface
Count Detect Logic
(Q7..Q4 = 10102)
Capture
Shift Register
S7..S0
Clock
Data Q3
!Q3
Display Register
D7..D0
Clock
Load

13. Xilinx XC95108 PC84 CPLD Display Register D7..D0 Clock Load
(Shift Register S7..S0)
(Capture)
(!Q3)
Binary-to-BCD
Converter
Hundreds Tens Units
7-Segment
Decoder
dpt 1 7
Voltage
Display
a..g

14. Pre-Lab:
Make a copy of your Bin9BCD.abl program from Group Homework # 5.
Make copies of your cadd3.abl, hex7seg.abl, and reg4bitg.abl from Labs 3 and 10.
Download a copy of the div16cnt.abl program from the class website.
Write an ABEL program, VM.abl, that provides the control signals for an ADC0831 chip and collects and displays the value of the measured voltage.

15. Lab:
Create a new project, Lab9a, and add a copy of your Bin9BCD.abl program. Simulate the Bin9BCD.abl program and print out a copy of the simulation report
Create a new project, Lab9b, and add a copy of your VM.abl program and copies of all embedded modules.
Generate a program file for your VM.abl program.
Build the ADC circuit on the breadboard and connect the circuit to the Xilinx XC95108 PC84 chip. Configure the PLDT-3 board and connect power to the PLDT-3 board.
Download and test your program.
Demonstrate your completed circuit to your lab instructor.