1. CSE598A Analog Mixed Signal CMOS Chip Design FM Mixer CMOS Realization Zhang Yi

2. Outline: Mixer’s Function in RF system Realize Gilbert Mixer by CMOS Technologies Project Schedule CSE598A Analog Mixed Signal CMOS Chip Design

3. Mixer ‘s Function in RF system CSE598A Analog Mixed Signal CMOS Chip Design Mixer

4. CSE598A Analog Mixed Signal CMOS Chip Design Mixer ‘s Function in RF system Up conversion in transmitter Down conversion in receiver

5. Critical points of Mixer: Image Frequency Conversion Loss Noise Figure Intermodulation Distortion Port-to-Port Isolation CSE598A Analog Mixed Signal CMOS Chip Design Mixer ‘s Function in RF system

6. CSE598A Analog Mixed Signal CMOS Chip Design Realize Gilbert Mixer by CMOS Technologies 1dB Compression point Intermodulation Distortion

7. Different Mixer’s Type: Diode Mixer FET Mixer : 1. Single-ended FET Mixer 2. Dual-gate FET Mixer 3. Differential FET Mixer 4. Gilbert Cell Mixer CSE598A Analog Mixed Signal CMOS Chip Design Realize Gilbert Mixer by CMOS Technologies

8. CSE598A Analog Mixed Signal CMOS Chip Design Realize Gilbert Mixer by CMOS Technologies Why Gilbert Cell? Advantages: (1) Both LO and RF are balanced, providing both LO and RF Rejection at the IF output. (2) All ports of the mixer are inherently isolated from each other. (3)Increased linearity compared to singly balanced. (4)Improved suppression of spurious products (all even order products of the LO and/or the RF are suppressed). (8)High intercept points.

9. CSE598A Analog Mixed Signal CMOS Chip Design Realize Gilbert Mixer by CMOS Technologies ParameterSpecificationUnits Frequency100MHz Noise Figure (DSB)<10dB IM3 Intercept Point (Input)>20dBm Voltage Gain>8dB Power consumption<100ohms Source impedance50ohms Load impedance500ohms Voltage Supply+/-1.5V Design criteria for the mixer

10. CSE598A Analog Mixed Signal CMOS Chip Design Project Schedule Week1: Schematic draft and hand calculation Week2: Schematic draw and simulation in Cadence and Hspice Week3: Optimize the schematic and simulation Week4: Optimize layout generated from schematic Week5: Simulated the extracted circuit from layout Week6:Optimize the layout/schematic Week7: Finalize the design.