1. ECE 448: Lab 6 Using PicoBlaze Fast Sorting

2. Part 1: Introduction to Lab 6 Part 2: Instruction Set of PicoBlaze-6 Part 3: Hands-on Session: OpenPICIDE Part 4: Lab 6 Exercise 1 Part 5: Lab 5 Demos Agenda for today

3. ECE 448 – FPGA and ASIC Design with VHDL Part 1 Introduction to Lab 6

4. 4ECE 448 – FPGA and ASIC Design with VHDL Sources P. Chu, FPGA Prototyping by VHDL Examples Chapter 14, Picoblaze Overview Chapter 15, Picoblaze Assembly Code Development Chapter 16, Picoblaze I/O Interface Chapter 17, Picoblaze Interrupt Interface K. Chapman, PicoBlaze for Spartan-6, Virtex-6, and 7-Series (KCPSM6)

6. 000 001 002... 0FE 0FF 100 101 102 103 104 105 106 107 108 109 1FE 1FF 255 x 8 DATA RAM MEM_BANK BUTTON SSD3 SSD2 LED PRNG_STATUS PRNG_CTRL MEM_BANK MEM_BANK: 7 6 5 4 3 2 1 0 A8 A8 – current memory bank number = the most significant bit of the address BUTTON: 7 6 5 4 3 2 1 0 A A – button active (bit cleared by reading register BUTTON or by interrupt_ack) BS – Select, BR – Right, BL – Left, BU – Up, BD - Down BDBUBLBR PRNG_STATUS: 7 6 5 4 3 2 1 0 D D – done: bit cleared by writing to register PRNG_CTRL, set after PRNG generates 255 8-bit numbers PRNG_CTRL: 7 6 5 4 3 2 1 0 I I – initialize: after 1 is written to this bit, PRNG generates 255 8-bit numbers, and the corresponding address (index) of each number SSD1 SSD0 SWITCH BS CCOUNT

7. SWITCH: 7 6 5 4 3 2 1 0 S0 S7-S0 – bits corresponding to the state of each switch S1S2S3S4S5S6S7 CCOUNT: 7 6 5 4 3 2 1 0 R R – reset the 64-bit Cycle Counter, and start counting clock cycles S – stop the Cycle Counter D – display the Cycle Counter (Switch S7 chooses between displaying Least Significant and Most Significant Word) S LED: 7 6 5 4 3 2 1 0 L0 L7-L0 – bits corresponding to the status of each LED L1L2L3L4L5L6L7 D

8. Task 1 – Browsing Mode (default mode) 00 01 02 03 04 05 …. FA FB FC FD FE 00 01 02 03 04 05 …. FA FB FC FD FE AddressData Current Address Two 7-Segment Displays (in hexadecimal notation) (SSD1-SSD0) Button Up = Increment Address Button Down = Decrement Address Value at Current Address 255x8 RAM Two 7-Segment Displays (in hexadecimal notation) (SSD3-SSD2)

9. Task 2 – Initialize 00 01 02 03 04 05 …. FA FB FC FD FE 25 87 94 26 B5 C6 …. 7A 5B 34 43 89 AddressData Button Left = Initialize with Pseudorandom Values Then, return to the browsing mode 255x8 RAM

10. 8-bit LCG (Linear Congruential Generator) with the period of 2 8 -1 R n+1 = a * R n + c (mod m) where R is the sequence of pseudorandom values, a is the multiplier, c is the increment and m is the modulus. R 0 will be the initial seed value. LCG generates one output per 1 clock cycle.

11. Task 3 – Sorting 00 01 02 03 04 05 …. FA FB FC FD FE 7F 67 53 44 38 2D …. B1 AA 91 80 AddressData Sorting signed numbers in the descending order 255x8 RAM

12. Task 4 – Cycle Count Display Mode During Sorting display: “ ---- ” on the Seven Segment Displays. After Sorting display: Number of clock cycles used (in the hexadecimal notation) #Cycles 15…0 - 16 least significant bits #Cycles 31..16 - 16 most significant bits Switch between these two values using switch S7 S7=0 : 16 least significant bits S7=1 : 16 most significant bits Pressing any button (other than Select) after sorting, brings the display back to the browsing mode.

13. Task 5 (Bonus) – Interrupts Modify your circuit in such a way that it generates an interrupt each time any button is pressed Modify your assembly language program accordingly, by replacing polling by an interrupt serving routine Consider using Register Bank switching in your interrupt service routine (if appropriate)

14. Contest for the Fastest Implementation of Sorting Bonus points will be awarded to students who perform sorting (correctly) using the smallest number of clock cycles. Possible optimizations: Faster sorting algorithms in software Efficient assembly language implementation Faster sorting algorithms in hardware Efficient hardware implementation

15. ECE 448 – FPGA and ASIC Design with VHDL Part 2 Instruction Set of PicoBlaze-6

16. 16 PicoBlaze-3 Programming Model ECE 448 – FPGA and ASIC Design with VHDL

17. 17 PicoBlaze-6 Programming Model ECE 448 – FPGA and ASIC Design with VHDL FFC FFD FFE FFF Bank A Bank B

18. Syntax and Terminology Syntax Example Definition sX KK PORT(KK) PORT((sX)) RAM(KK) s7 ab PORT(2) PORT((sa)) RAM(4) Value at register 7 Value ab (in hex) Input value from port 2 Input value from port specified by register a Value from RAM location 4

19. Addressing modes Direct mode ADD sa, sf INPUT s5, 2a sa + sf  sa PORT(2a)  s5 Indirect mode STORE s3, (sa) INPUT s9, (s2) s3  RAM((sa)) PORT((s2))  s9 s7 – 07  s7 s2 + 08 + C  s2 Immediate mode SUB s7, 07 ADDCY s2, 08

20. Arithmetic Instructions (1) IMM, DIR C Z Addition ADD sX, sY sX + sY => sX ADD sX, KK sX + KK => sX ADDCY sX, sY sX + sY + CARRY => sX ADDCY sX, KK sX + KK + CARRY => sX

21. Arithmetic Instructions (2) Subtraction SUB sX, sY sX – sY => sX SUB sX, KK sX – KK => sX SUBCY sX, sY sX – sY – CARRY => sX SUBCY sX, KK sX – KK – CARRY => sX IMM, DIR C Z

22. Test and Compare Instructions TEST TEST sX, sY sX and sY => none TEST sX, KK sX and KK => none COMPARE COMPARE sX, sY sX – sY => none COMPARE sX, KK sX – KK => none C Z IMM, DIR C = odd parity of the result

23. Data Movement Instructions (1) LOAD LOAD sX, sY sY => sX LOAD sX, KK KK => sX IMM, DIR C Z -

24. FETCH FETCH sX, KK RAM(KK) => sX FETCH sX, (sY) RAM((sY)) => sX Data Movement Instructions (2) DIR, IND C Z - STORE STORE sX, KK sX => RAM(KK) STORE sX, (sY) sX => RAM((sY)) DIR, IND -

25. Example 1: Clear Data RAM ;========================================================= ; routine: clr_data_mem ; function: clear data ram ; temp register: data, s2 ;========================================================= clr_data_mem: load s2, 40 ;unitize loop index to 64 load s0, 00 clr_mem_loop: store s0, (s2) sub s2, 01 ;dec loop index jump nz, clr_mem_loop ;repeat until s2=0 return

26. Data Movement Instructions (3) INPUT INPUT sX, KK sX <= PORT(KK) INPUT sX, (sY) sX <= PORT((sY)) OUTPUT OUTPUT sX, KK PORT(KK) <= sX OUTPUT sX, (sY) PORT((sY)) <= sX DIR, IND C Z -

27. Edit instructions - Shifts *All shift instructions affect Zero and Carry flags

28. Edit instructions - Rotations *All rotate instructions affect Zero and Carry flags

29. Program Flow Control Instructions (1) JUMP AAA PC <= AAA JUMP C, AAA if C=1 then PC <= AAA else PC <= PC + 1 JUMP NC, AAA if C=0 then PC <= AAA else PC <= PC + 1 JUMP Z, AAA if Z=1 then PC <= AAA else PC <= PC + 1 JUMP NZ, AAA if Z=0 then PC <= AAA else PC <= PC + 1

30. Program Flow Control Instructions (2) CALL AAA TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA CALL C | Z, AAA if C | Z =1 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1 CALL NC | NZ, AAA if C | Z =0 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1

31. Program Flow Control Instructions (3) RETURN PC <= STACK[TOS] + 1; TOS <= TOS - 1 RETURN C | Z if C | Z =1 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1 RETURN NC | NZ if C | Z =0 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1

32. Subroutine Call Flow

33. ECE 448 – FPGA and ASIC Design with VHDL Part 3 Hands-on Session: OpenPICIDE

34. 34 PicoBlaze Development Environments ECE 448 – FPGA and ASIC Design with VHDL

35. 35 KCPSM6 Assembler Files ECE 448 – FPGA and ASIC Design with VHDL KCPSM6.EXE

36. 36 Directives of Assembly Language ECE 448 – FPGA and ASIC Design with VHDL Equating symbolic name for an I/O port ID. keyboard DSIN $0E switch DSIN $0F LED DSOUT $15 N/A

37. 37 Differences between Mnemonics of Instructions ECE 448 – FPGA and ASIC Design with VHDL

38. 38 Differences between Mnemonics of Instructions ECE 448 – FPGA and ASIC Design with VHDL

39. 39 Differences between Programs ECE 448 – FPGA and ASIC Design with VHDL

40. 40 ECE 448 – FPGA and ASIC Design with VHDL Example & Demo of Tools

41. 41 ECE 448 – FPGA and ASIC Design with VHDL Part 4 Lab 6 Exercise 1

42. 42 Develop an assembly language implementation of a Linear Congruential Generator (LCG) producing a sequence of 8-bit pseudo-random numbers. Then, use OpenPICIDE to debug and simulate your program. Recurrence relation R n+1 = a * R n + c (mod m), where  m = 2 8  a=0x11  c=0x9D  R 0 =0xD7 Additionally, assume that * represents an unsigned multiplication Linear Congruential Generator (LCG)

43. 43 ECE 448 – FPGA and ASIC Design with VHDL Example of a function in the PicoBlaze assembly language

44. 44 Notation a Multiplicand a k-1 a k-2... a 1 a 0 x Multiplier x k-1 x k-2... x 1 x 0 p Product (a  x) p 2k-1 p 2k-2... p 2 p 1 p 0

45. 45 Multiplication of two 4-bit unsigned binary numbers Partial Product 0 Partial Product 1 Partial Product 2 Partial Product 3

46. 46 Unsigned Multiplication – Basic Equations x =  x i  2 i i=0 k-1 p = a  x p = a  x =  a  x i  2 i = = x 0 a2 0 + x 1 a2 1 + x 2 a2 2 + … + x k-1 a2 k-1 i=0 k-1

47. 47 Iterative Algorithm for Unsigned Multiplication Shift/Add Algorithm p = a  x = x 0 a2 0 + x 1 a2 1 + x 2 a2 2 + … + x k-1 a2 k-1 = (...((0 + x 0 a2 k )/2 + x 1 a2 k )/2 +... + x k-1 a2 k )/2 = k times = p (0) = 0 p = p (k) p (j+1) = (p (j) + x j a 2 k ) / 2 j=0..k-1

48. 48 Iterative Algorithm for Unsigned Multiplication Shift/Add Algorithm p = a  x = x 0 a2 0 + x 1 a2 1 + x 2 a2 2 + … + x 7 a2 7 = (...((0 + x 0 a2 8 )/2 + x 1 a2 8 )/2 +... + x 7 a2 8 )/2 = 8 times = p (0) = 0 p = p (k) p (j+1) = (p (j) + x j a 2 8 ) / 2 j=0..7

49. 49 Unsigned Multiplication Computations pHpH pLpL 8 bits p x j a 8 bits pHpH pLpL pHpH pLpL C p (j+1) 2 p (j+1) p (j) + x j a 2 8 >> 1 PicoBlaze Registers p H = s5p L = s6 a = s3 x = s4 + C

50. 50 Unsigned Multiplication Subroutine (1) ;========================================================= ; routine: mult_soft ; function: 8-bit unsigned multiplier using ; shift-and-add algorithm ; input register: ; s3: multiplicand ; s4: multiplier ; output register: ; s5: upper byte of product ; s6: lower byte of product ; temporary register: ; s2: index j ;=========================================================

51. 51 Unsigned Multiplication Subroutine (2) mult_soft: load s5, 00 ; clear pH load s2, 08 ; initialize loop index mult_loop: sr0 s4 ; shift lsb of x to carry jump nc, shift_prod ; x_j is 0 add s5, s3 ; x_j is 1, pH=pH+a shift_prod: sra s5 ; shift upper byte pH right, ; carry to MSB, LSB to carry sra s6 ; shift lower byte pL right, ; lsb of pH to MSB of pL sub s2, 01 ; dec loop index jump nz, mult_loop ;repeat until i=0 return

52. 52 ECE 448 – FPGA and ASIC Design with VHDL Part 5 Lab 5 Demos