1. 1 Class Presentation on Binary Moment Diagrams by Krishna Chillara Base Paper: “Verification of Arithmetic Circuits with Binary Moment Diagrams” by Randal E. Bryant and Yirng-An Chen

2. 2 Outline  Introduction  Prior work – BDDs, MTBDDs  Binary Moment Diagrams (BMDs) Construction rules of *BMDs *BMDs - Illustration AND, OR, XOR using *BMDs Word level Operations using *BMDs  Verification using *BMDs  Summary

3. 3 Introduction  Some function representations discussed in this course Sum of the Product form Factored forms Truth Table Binary Decision Diagrams  Binary Decision Diagrams Simple in representing and manipulating Boolean functions Reduced Ordered BDDs are canonical (useful for verification)  Drawbacks of BDDs Does not handle functions with non-Boolean range Bit level representation but specs are in word level Not good for representing arithmetic operations Consider a 32 bit multiplication using BDDs M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

4. 4 Prior work - BDDs  Boolean function f decomposed in terms of a variable x can be represented by Shannon expansion as f = (x f x ) (x’  f x’ )  Function decomposed into positive and negative co- factors at the node variable x f x = f(x=1) f x ’ = f(x=0)  BDDs Boolean  Boolean Point-wise decomposition (Decision) The output is Boolean Decision at every node and proceed

5. 5 Prior work - MTBDDs  MTBDDs Multi Terminal BDDs Extending BDDs to allow integer leaf values Point-wise decomposition based on Shannon expansion

6. 6 Problem Statement  To find a data structure that can map Boolean variables to integers in a compact form This helps in representing the arithmetic operations Word level operations easy to handle Ex: Bit level Multiplier vs Word level Specs are in word level

7. 7 Binary Moment Diagrams (BMDs)  Modified Shannon Expansion Boolean variable treated as a binary (0,1) integer variable Complement of x modeled as (1-x) Now the function can be represented as f = x f x=1 + (1-x) f x=0 = f x=0 + x (f x=1 – f x=0 ) = f x=0 + x f x + is addition here  Function is branched into two components Constant Component Linear Component Moment based decomposition M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

8. 8 Reading Binary Moment Diagrams  BMDs Linear moment decomposition Dotted node represents constant moment and solid line represents linear moment f = const + var* lin_moment f = k + y*g g = 2 + 4*z k = 8 + (-20)*z Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

9. 9 Multiplicative BMD (*BMD)  BMDs simply encode the numerical values into terminal vertices.  In a *BMD edge weights are used to share any common sub-expressions.  *BMDs Not decision diagrams as they are based on the moment decomposition Multiplicative diagrams – each path is a product of nodes and the edge weights

10. 10 *BMD reduction rules  Irredundancy When a linear moment of at a node v is 0, the function has only a constant term and thus does not depend on v. Hence node v can be removed.  Merge the identical sub-graphs Similar to BDDs Two nodes with same index variable and having same two moments can be merged. M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

11. 11 Normalization of weights  Rules imposed on manipulating edge weights to make the graph canonical  Normalized by factoring out gcd of the argument weights w=gcd(w l (x),w h (x)) Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

12. 12 Illustration - BMD  f=8-20z+2y+4yz+12x+24xz+15xy  Variable order (say) x,y,z  f= f x’ + x f x Linear = f x Constant = f x’ x 12 y z 42-20 8 y zz 2415 8+2y+4yz-20z12+15y+24z 8-20z 4z+2 12+24z

13. 13 Illustration - *BMD  f=8-20z+2y+4yz+12x+24xz+15xy  Variable order (say) x,y,z  f= f x’ + x f x Linear = f x Constant = f x’ x 12 y z 42-20 8 y zz 24 15 8+2y+4yz-20z 12+15y+24z 8-20z 4z+2 12+24z 2-51212 4 22 2 12 15 3 45

14. 14 Illustration - *BMD  f=8-20z+2y+4yz+12x+24xz+15xy  Variable order (say) x,y,z  Introducing the edge weights x 1 y z 21-5 2 y zz 21 4+y+2yz-10z 4+5y+8z 2-5z 2z+1 23 2 4 8+2y+4yz-20z 12+15y+24z 4-10z 8z+4 5

15. 15 Illustration - *BMD  f=8-20z+2y+4yz+12x+24xz+15xy = 8-20z+2y (1+2z) + 12x(1+2z) +15xy  Variable order (say) x,y,z  *BMD after reduction x y z 1 y z 4+y+2yz-10z 4+5y+8z 2-5z 2z+1 23 2 4 -5 2 2 5

16. 16 Illustration BMD and *BMD  Unsigned integer: X = 8x 3 + 4x 2 + 2x 1 + x 0 1 0 x0 x1 x2 1 2 4 x3 8 *BMD x3 8 x2 x1 x0 421 0 BMD Slide taken from Prof. Ciesielski’s TED presentation.

17. 17 Representation of Integers  Unsigned – sum of the weighted bits  Signed – Two’s complement, Sign- Magnitude Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

18. 18 Decisions Making  In a real scenario we might still have to make a decision at some point (Boolean connectors)  BMDs will try to implement Boolean in terms of arithmetic expression  MUX: y = (A (and) s’ ) OR (B (and) s) MUL MUX

19. 19 Representation of Boolean functions  NOT : x’ = (1-x)  AND: x  y  OR: x+y-(x  y)  XOR: x+y-2(x  y) x 1 x y 10 x 0 y y 1 x 0 y y 1 -2 NOTAND OR XOR M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification. XyORX+Y 0000 0111 1011 1112

20. 20 Representation of word level operations - Addition  SUM X+Y  Both X and Y here are 3 bit wide  X= 4x 2 +2x 1 +x 0 Y= 4y 2 +2y 1 +y 0  X+Y = (4x 2 +2x 1 +x 0 )+(4y 2 +2y 1 +y 0 ) = 4*(x 2 +y 2 ) + 2*(x 1 +y 1 ) + (x 0 +y 0 )  Linear with number of bits 10 y0 x0 y1 1 1 2 x1 2 y2 x2 4 4 M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

21. 21 Bit level representation of addition  Derived using gate level representation of the circuit  Sum using XORs and carry using AND, OR gates Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

22. 22 Representation of word level operations - Product  Product X*Y  Both X and Y here are 3 bit wide  X= 4x 2 +2x 1 +x 0 Y= 4y 2 +2y 1 +y 0  X*Y = (4x 2 +2x 1 +x 0 )*(4y 2 +2y 1 +y 0 ) = 4x 2 *(4y 2 +2y 1 +y 0 ) + 2x 1 *(4y 2 +2y 1 +y 0 ) + x 0 *(4y 2 +2y 1 +y 0 )  Variable order x 2 x 1 x 0 y 2 y 1 y 0  Linear with number of bits 10 y0 y1 y2 1 2 4 x0 x1 x2 4 2 1 M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

23. 23 Verification using BMDs  Goal: To prove equivalence between the bit level circuit and word level specification Word level – Word level Bit level – Word level Hierarchical  Circuit output interpreted as word should match the specification when applied to word level interpretations of the input Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

24. 24 Summary  *BMDs Maps Boolean to Integers Canonical Equivalence check  Limitations Satisfiability Cannot be determined directly like in BDDs Outputs are integer Cannot split output into individual bits What if you want to look into a particular output bit?

25. 25 References  [1] Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995  [2] M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification

26. 26 Thank You!