1. Asynchronous VHDL Extensions Joshua & Ravi FTL Systems Nothing in this presentation implies an offer for sale. FTL Systems is willing to provide IEEE Inc. a non-exclusive, cost-free license to use specific aspects of VHDL-X related to select aspects of asynchronous VHDL. The license does not include patent or copyright for other aspects of VHDL-X. The full VHDL-X LRM is FTL Systems Proprietary. Funded in part by DARPA’s ACS, NeoCAD & CLASS programs

2. Objective Enable design of asynchronous / clock-less systems with less design time and greater integrity than clocked systems, facilitate hybrid / GALS systems Maintain full upward compatibility with VHDL-2002 semantics

3. Key Base Feature Requirements Overloading of Signal Assignment Operator Overloading of array index operator Effective skew control for non-delay insensitive asynchrony Designation of explicit sensitivity lists within concurrent process equivalents Related extensions to PSL/Sugar