1. OSes: 2. Structs 1 Operating Systems v Objective –to give a (selective) overview of computer system architectures Certificate Program in Software Development CSE-TC and CSIM, AIT September -- November, 2003 2. Computer-System Structures (Ch. 2, S&G)

2. OSes: 2. Structs 2 Contents 1.A Modern Computer System 2.Interrupts 3.I/O 4.Caching 5.Protection

3. OSes: 2. Structs 3 1. A Modern Computer System Fig 2.1, p.24 CPU disk controller printer controller tape-drive controller memory controller memory Line Printer system bus continued I/O controller

4. OSes: 2. Structs 4 v CPU and device controllers (drivers) can execute concurrently. v Access to shared memory must be controlled. v A hard-wired bootstrap program loads and starts the OS kernel.

5. OSes: 2. Structs 5 2. Interrupts v Modern OSes are driven by interrupts (traps) sent when events occur in hardware or software. v Types of events: –completion of I/O, division by 0, system calls, etc. continued

6. OSes: 2. Structs 6 v An interrupt causes the OS to stop its current task, and switch execution to an interrupt-processing routine. v At the end of the routine, the old task is resumed –the old task’s details must be stored during the interrupt processing continued

7. OSes: 2. Structs 7 v The addresses of the interrupt routines are stored in a fixed segment of memory (an interrupt vector). v The OS selects a routine from the interrupt vector based on the ‘type’ of the interrupt it received. continued

8. OSes: 2. Structs 8 v Features of interrupts: –disabling of other interrupts during interrupt processing –prioritisation

9. OSes: 2. Structs 9 System Calls v System calls are implemented using interrupts. Fig 2.9, p.44 : system call n : case n : read : user program resident monitor return 3 trap to monitor 1 perform I/O 2

10. OSes: 2. Structs 10 3. I/O v Synchronous I/O –the user process waits during I/O processing v Asynchronous I/O –control returns to the user without waiting for the I/O to complete

11. OSes: 2. Structs 11 I/O Forms Fig. 2.3, p.27 requesting process device driver interrupt handler hardware data transfer user kernel time Synchronous requesting process device driver interrupt handler hardware data transfer user kernel time Asynchronous

12. OSes: 2. Structs 12 3.1. Synchronous I/O v Waiting is done either with: –a special wait instruction –a busy-wait loop, such as: loop: jmp loop v A busy-wait generates instruction fetches, and so may lead to contention with the I/O. v Only one I/O process involved.

13. OSes: 2. Structs 13 3.2. Asynchronous I/O v Big advantage: the CPU is not affected while slow I/O is carried out. v Many I/O requests can be in action at once –the implementation requires an I/O device status table

14. OSes: 2. Structs 14 I/O Device Status Table Fig 2.4, p.28 dev: card reader 1 status: idle dev: line printer 3 status: busy dev: disk unit 1 status: idle dev: disk unit 2 status: idle dev: disk unit 3 status: busy : file: xxx op: read addr: 23456 length: 2000 file: yyy op: write addr: 6543 length: 500 PID: 3445 addr: 34556 length: 1345

15. OSes: 2. Structs 15 3.3. Direct Memory Access (DMA) v Device controllers transfer data blocks to/from memory directly, bypassing the CPU –only one interrupt generated per block –much faster than interrupt driven character transfer

16. OSes: 2. Structs 16 3.4. Memory Mapped I/O v I/O device registers is mapped to memory so that reads/writes to those memory addresses go straight to the device –used for fast and frequently used device –e.g. video controller, serial port

17. OSes: 2. Structs 17 4. Caching v The cache is fast memory between the CPU and main memory –the CPU looks in the cache first for data –new data taken from main memory is also placed in the cache for quick access next time v Instruction caching v Cache management –can affect performance drastically

18. OSes: 2. Structs 18 Cache Coherency v Must ensure that the data in the cache is always the same as its original version in main memory. v Complicated by multiprocessor and distributed environments –several caches, replicated memory

19. OSes: 2. Structs 19 5. Protection v 5.1. Dual-mode Operation v 5.2. Memory Protection v 5.3. CPU Protection

20. OSes: 2. Structs 20 5.1. Dual-mode Operation v User mode v Monitor mode –supervisor mode, root, superuser, system mode, priveleged mode v Implemented in hardware v OS always runs in monitor mode

21. OSes: 2. Structs 21 5.2. Memory Protection v The interrupt vector must be protected from modification by users. v The interrupt processing routines must be similarily protected.

22. OSes: 2. Structs 22 Partitioning Memory Fig 2.7, p.40 monitor job 1 job 2 job3 job4 0 256000 300040 420940 880000 1024000 300040 base register 120900 limit register

23. OSes: 2. Structs 23 v Only addresses within the job’s memory space are accessible. CPU >=< basebase + limit trap to OS monitor -- addressing error memory address yes no Fig 2.8, p.41

24. OSes: 2. Structs 24 5.3. CPU Protection v Each process is interrupted after a fixed time –this breaks infinite loops in poor code which would otherwise hog the CPU –allows the OS to time-slice users by context switching