© 2004 Xilinx, Inc. All Rights Reserved Hardware Design.

Hardware Design - 3 - 3 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Objectives After completing this module, you will be able to: List the functionality that defines an arbiter, a master, and a slave List various buses available in MicroBlaze  and PowerPC  processors Discuss the six configurations of the MicroBlaze processor Discuss the JTAG interface in Virtex-II Pro  devices

Hardware Design - 3 - 4 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Buses 101: Arbiter, Master, Slave – PLB – OPB – DCR – OCM – LMB MicroBlaze Processor Programmer’s Model MicroBlaze Configurations PowerPC Processor Programmer’s Model Reset Logic in PowerPC JTAG Configurations in Virtex-II Pro

Hardware Design - 3 - 5 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Buses 101 A bus is a multi-wire path on which related information is delivered – Address, data, and control buses Processor and peripherals communicate through buses Peripherals may be classified as – Arbiter, master, slave, or master/slave (bridge) Master Master/ Slave Master Arbiter

Hardware Design - 3 - 6 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Buses 101 Bus masters have the ability to initiate a bus transaction Bus slaves can only respond to a request Bus arbitration is a three-step process: – A device requesting to become a bus master asserts a bus request signal – The arbiter continuously monitors the request and outputs an individual grant signal to each master, according to the master’s priority scheme and the state of the other master requests at that time – The requesting device samples its grant signal until the master is granted access. The master then initiates a data transfer between the master and a slave when the current bus master releases the bus Arbitration mechanisms – Fixed priority, round-robin, a hybrid

Hardware Design - 3 - 7 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only PowerPC Bus Example PPC405 ISOCM DSOCM DSPLB ISPLB INTC BRAM DDR PLB ARB BRAM SDRAM DCR PLB2OPB IIC OPB ARB GPIO UART Ethernet LCD BRAM INTC OPB2PLB ISOCM Bus Data- 64 bits Address- 32 bits PLB Bus Data- 64 bits Address- 32 bits OPB Bus Data- 32 bits Address- 32 bits DCR Bus Data- 32 bits Address- 10 bits DSOCM Bus Data- 32 bits Address- 32 bits

Hardware Design - 3 - 8 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only MicroBlaze Bus Example MicroBlaze DOPB BRAM DLMB IIC OPB ARB GPIO UART Ethernet LCD BRAM INTC IOPB ILMB Ext Mem ILMB Bus DLMB Bus DOPB Bus IOPB Bus All buses are 32 bits

Hardware Design - 3 - 9 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only CoreConnect The IBM CoreConnect  standard provides three buses for interconnecting cores, library macros, and custom logic: – Processor Local Bus (PLB) – On-chip Peripheral Bus (OPB) – Device Control Register (DCR) bus IBM offers a no-fee, royalty-free CoreConnect architectural license – Licenses receive the PLB arbiter, OPB arbiter, and PLB/OPB bridge designs along with bus-model toolkits and bus-functional compilers for the PLB, OPB, and DCR buses – Required only if you create your own CoreConnect peripheral or you are using Bus Functional Model (BFM)

Hardware Design - 3 - 11 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only PLB Bus – Connection infrastructure for high-bandwidth master and slave devices – Fully synchronous to one clock – Centralized bus arbitration—PLB arbiter – 64-bit data bus – Addresses high-performance, low-latency, and design-flexibility issues through: Decoupled address and read and write data buses with split transaction capability Concurrent read and write transfers yielding a maximum bus utilization of two data transfers per clock Address pipelining that reduces bus latency by overlapping a new write request with an ongoing write transfer and up to three read requests with an ongoing read transfer Ability to overlap the bus request and grant protocol with an ongoing transfer

Hardware Design - 3 - 12 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only PLB Interconnect / Architecture One to 16 PLB masters, each connect all of their signals to the PLB arbiter The PLB arbiter multiplexes signals from masters onto a shared bus to which all the inputs of the slaves are connected One to n PLB slaves OR together their outputs to drive a shared bus back to the PLB arbiter The PLB arbiter handles bus arbitration and the movement of data and control signals between masters and slaves

Hardware Design - 3 - 13 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only PLB Arbiter PLB master – Arbitration support for up to 16 masters – The number of PLB masters is configurable via a design parameter – PLB address pipelining – Three-cycle arbitration – Four levels of dynamic master request priority PLB slave – Supports up to 16 slaves – The number of PLB slaves is configurable via a design parameter – No external OR gates are required for PLB slave input signals PLB architecture compliant

Hardware Design - 3 - 14 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Arbitration Priority During the bus arbitration cycle, the bus arbitration control unit uses the M_priority[0:1] signals to determine which master is granted the bus Only the priority inputs of masters with their respective M_request[n] signal asserted are used in determining the highest request priority Priority to each device is automatically assigned as the masters are added Priorities can be changed in the MHS file by using the following syntax – BUS_INTERFACE MOPB = instance_name POSITION = integer – The integer is a positive number, with 1 being for the highest priority

Hardware Design - 3 - 15 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Resolving Priority The Xilinx PLB implements a fixed-priority scheme to handle “tie” situations, which occur when two or more masters have the same level of request priority

Hardware Design - 3 - 16 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only PLB Bridge The PLB-to-OPB bridge translates PLB transactions into OPB transactions This bridge functions as a slave on the PLB side and a master on the OPB side The bridge contains a DCR slave interface to provide access to its bus error status registers The bridge is necessary in systems where a PLB master device, such as a CPU, requires access to OPB peripherals

Hardware Design - 3 - 18 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only OPB Bus The OPB bus decouples lower bandwidth devices from the PLB It is a less complex protocol than PLB – No split transaction or address pipelining capability Centralized bus arbitration—OPB arbiter Connection infrastructure for the master and slave peripheral devices The OPB bus is designed to alleviate system performance bottlenecks by reducing capacitive loading on the PLB – Fully synchronous to one clock – Shared 32-bit address bus, shared 32-bit data bus – Supports single-cycle data transfers between the master and the slaves – Supports multiple masters, determined by arbitration implementation – The bridge function can be the master on the PLB or OPB

Hardware Design - 3 - 19 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only OPB Bus Supports 16 masters and an unlimited number of slaves (limited by the expected performance) The OPB arbiter receives bus requests from the OPB masters and grants the bus to one of them – Fixed and dynamic (LRU) priorities Bus logic is implemented with AND-OR logic. Inactive devices drives zeros Read and write data buses can be separated to reduce loading on the OPB_DBus signal

Hardware Design - 3 - 21 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only DCR Bus Device-control register bus – IBM CoreConnect  standard – Used to talk to control registers (1024 total) – 32-bits-wide data  all cycles word-oriented – Supports read and write only, no burst cycles – Simple acknowledgement termination – CPU supports special privileged instructions for access to the DCR Normal DCR requires special CPU assembly code to access – There is a “fixed” 1024-word I/O space – Must be privilege mode to access registers – Not easy to use without special C function headers or inline ASM

Hardware Design - 3 - 22 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only DCR Bus C405DCRABUS C405DCRDBUSOUT C405DCRREAD DCRC405ACK DCRC405DBUSIN C405DCRWRITE PPC405DCR Devices dcr_Ack dcr_Write dcr_Read dcr_RdData dcr_WrData dcr_ABus dcr_Clk

Hardware Design - 3 - 23 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Memory Mapped DCR DCR bridges allow memory mapping of DCR space anywhere within the system memory – OPB DCR bridge – Allows DCR devices to exist within 4 KB of contiguous space – Must be accessed on word boundaries and one word at a time – Easier to use, but it requires a PLB and OPB transaction

Hardware Design - 3 - 25 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only OCM Bus 405 OCM I/Fs – PPC405 has a separate interface used for high-speed access of on-chip memory – PPC405 presents address on both the PLB bus and the OCM bus – Addresses cannot exist in both PLB and OCM space – OCM addresses are non-cacheable, leaving the cache resources for the PLB accesses The processor block contains the OCM controllers – The processor block contains dedicated controllers to interface between the OCM I/F and FPGA BRAM – There are separate independent controllers for the I-side and D-side to provide higher performance All signals are in big-endian format

Hardware Design - 3 - 26 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only OCM Bus Features – Independent 16-MB logical space for each of the DSOCM and ISOCM 16 MB must be reserved regardless of actual memory used – 64-bit ISOCM and 32-bit DSOCM – Up to 128 KB / 64 KB (ISOCM / DSOCM) using programmable BRAM aspect ratios – Programmable processor versus BRAM clock ratio – DSBRAM load: BRAM initialization (Data2MEM), CPU, and FPGA using dual-port BRAM – ISBRAM load: BRAM initialization (Data2MEM) and DCR – CPU DCR-accessible registers

Hardware Design - 3 - 27 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only OCM Bus Benefits – Avoids loads into cache, reducing pollution and thrashing – Has fast-fixed latency of execution – On the D-side, dual-port BRAM enables a bidirectional data connection with the processor Sample uses – I-side: Interrupt service routines, boot-code storage – D-side: Scratch-pad memory, bidirectional data transfer

Hardware Design - 3 - 28 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Bus Timing Use timing constraints to determine which ratio to use *There are two independent clocks for each OCM controller: – BRAMDSOCMCLK – BRAMISOCMCLK PLB CLKOPB CLKDCR CLKOCM CLK * Transaction synchronous withProcessor clockPLB clockProcessor clock Clock ratio1:1 to 16:11:1 to 4:11:1 to 8:11:1 to 4:1 ExampleProcessor clock at 300 MHz, PLB at 100 MHz PLB at 100 MHz, OPB at 50 MHz Processor clock at 300 MHz, DCR at 100 MHz Processor clock at 300 MHz, OCM at 150 MHz

Hardware Design - 3 - 30 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only LMB Bus The LMB provides single-cycle access to on-chip dual-port block RAM LMB provides simple synchronous protocol for efficient block RAM transfers LMB provides maximum guaranteed performance of 125 MHz in Virtex- II  devices for local-memory subsystem DLMB: Data interface, local memory bus (BRAM only) ILMB: Instruction interface, local memory bus (BRAM only)

Hardware Design - 3 - 31 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only LMB Bus Timing Rules for generating an LMB clock – The MB, LMB, and OPB clock must be the same clock Use timing constraints to determine the clock speed

Hardware Design - 3 - 35 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Review Questions What is the advantage of using the memory-mapped DCR component? What is the disadvantage of using the memory-mapped DCR component? Which buses are included in the CoreConnect  standard? What is the maximum performance of the LMB in a Virtex  -II device?

Hardware Design - 3 - 36 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Answers What is the advantage of using the memory-mapped DCR component? – Does not require inline ASM instructions to access the bus What is the disadvantage of using the memory-mapped DCR component? – Requires a PLB and an OPB transaction Which buses are included in the CoreConnect  standard? – PLB, OPB, and DCR What is the maximum performance of the LMB in a Virtex  -II device? – 125 MHz

Hardware Design - 3 - 38 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only MicroBlaze Processor Embedded soft RISC Processor – 32-bit data – 32-bit instruction word (three operands and two addressing modes) – 32 registers (32-bit wide) – 3 pipe stages (single issue) – Big-endian format Buses – Full Harvard-architecture – OPB (CoreConnect  standard), instruction and data – LMB for connecting to local BRAM (faster), instruction and data

Hardware Design - 3 - 39 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only MicroBlaze Processor ALU – Uses hardware multipliers in Virtex  -II architecture – Barrel shifter Program counter Instruction decode 32-bit registers Instruction cache – Configurable size—2 KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB – Speeds up a typical program running from 60 nS (16 MHz) external memory by three to six times Bus interfaces – Instruction and data

Hardware Design - 3 - 40 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only MicroBlaze Performance 150 MHz on Virtex-II Pro  (-6) devices 100 Dhrystone-MIPs using LMB BRAM All instruction takes one clock cycle, except… – Load and store (two clock cycles) – Multiply (two clock cycles) – Branches (three clock cycles, can be one clock cycle) Approximately 900 LUTs (450 slices, 110 Virtex  -II CLB)

Hardware Design - 3 - 41 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only MicroBlaze Memory Space Memory and peripherals – The MicroBlaze  processor uses 32-bit addresses Special addresses – MicroBlaze processors must have user-writable memory from 0x00000000 through 0x00000017 BRAM size limits – The amount of BRAM memory that can be assigned is limited – The largest supported BRAM memory size for Virtex  and Virtex-E is 16 kilobytes; for Virtex-II, it is 64 kilobytes 0x0000_0000 0x0000_0008 0x0000_0010 0xFFFF_FFFF 0x0000_0018 Reset Address Exception Address Interrupt Address LMB Memory OPB Memory Peripherals

Hardware Design - 3 - 44 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Configuration 1 Large external instruction memory Fast internal instruction memory (BRAM) Large external data memory Fast internal data memory (BRAM)

Hardware Design - 3 - 46 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Configuration 3 Fast internal instruction memory (BRAM) Large external data memory Fast internal data memory (BRAM)

Hardware Design - 3 - 47 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Configuration 4 Large external instruction memory Fast internal instruction memory (BRAM) Large external data memory

Hardware Design - 3 - 52 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only PowerPC Processor A 32-bit implementation of the PowerPC  embedded-environment architecture Support for embedded-systems applications – Flexible memory management – Multiply and accumulate instructions for computationally intensive applications – Enhanced debug capabilities – 64-bit time base – Programmable interval (PIT), fixed interval (FIT), and watchdog timers Performance-enhancing features – Static branch prediction – Five-stage pipeline – Hardware multiply/divide for faster integer arithmetic – Enhanced string and multiple-word handling – Minimized interrupt latency

Hardware Design - 3 - 53 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only PowerPC Memory and peripherals – PPC405 uses 32-bit addresses Special addresses – Every PowerPC  system should have the boot section starting at 0xFFFFFFFC – The default program space occupies a contiguous address space from 0xFFFF0000 to 0xFFFFFFFF – If interrupt handlers are present,.Vectors should start at 64K boundary 0x0000_0000 0xFFFF_0000 0xFFFF_FFFC Peripherals PLB/OPB Memory Reset Address

Hardware Design - 3 - 55 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Reset Interface NameInstructions RSTC405RESETCOREInput—Resets the data and instruction caches RSTC405RESETCHIPInput—Resets the entire core and on-chip peripherals RSTC405RESETSYSInput—Resets the entire system, including core, FPGA, and external components C405RSTCORERESETREQOutput—Indicates data and instruction cache reset C405RSTCHIPRESETREQOutput—Indicates reset for on-chip peripheral resets C405RSTSYSRESETREQOutput—Indicates reset for the entire system

Hardware Design - 3 - 56 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only PROC_SYS_RESET Asynchronous external reset input is synchronized with the clock Asynchronous auxiliary external reset input is synchronized with the clock Both the external and auxiliary reset inputs are selectable active-High or active-Low Selectable minimum pulse width for reset inputs to be recognized Selectable load equalizing DCM-locked input Power-on reset generation Sequencing of reset signals coming out of reset: – First — Bus structures come out of reset PLB and OPB arbiter and bridges for example – Second — Peripherals come out of reset 16 clocks later UART, SPI, and IIC, for example – Third — The CPUs come out of reset 16 clocks after the peripherals

Hardware Design - 3 - 57 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only PROC_SYS_RESET Attributes Attribute DescriptionDefault C_EXT_RST_WIDTH Specifies the number of clocks wide a change on Ext_Reset_In must be before the change is detected and used 4 C_AUX_RST_WIDTH Specifies the number of clocks wide a change on Aux_Reset_In must be before the change is detected and used 4 C_EXT_RESET_HIGH Sets the value for which Ext_Reset_In causes a reset. If this parameter is set to a 1, when Ext_Reset_In is high on a rising edge of a clock, a reset is initiated 1 C_AUX_RESET_HIGH Sets the value for which Aux_Reset_In causes a reset. If this parameter is set to a 0, when Aux_Reset_In is low, a reset is initiated 1 C_NUM_BUS_RST Used to generate additional Bus_Struct_Reset signals. This helps with signal loading and routing. In general, each bus should have its own Bus_Struct_Reset signal 1 C_NUM_PERP_RST Used to generate additional Peripheral_Reset signals. This helps with signal loading and routing. In general, every peripheral should have its own Peripheral_Reset signal 1

Hardware Design - 3 - 58 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only PROC_SYS_RESET If C_EXT_RST_WIDTH is set to five and C_EXT_RESET_HIGH is set to zero, then the Ext_Reset_In must become active and stay active for at least five clocks before a reset is initiated 123456

Hardware Design - 3 - 60 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only JTAG TAP Options At design time, you have control over whether each of the PowerPC  JTAG TAP (in case of multiple PowerPCs) is incorporated into the FPGA JTAG TAP chain after FPGA configuration, or whether it remains a separate chain This is accomplished by instantiating or not instantiating the dedicated JTAGPPC block

Hardware Design - 3 - 61 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only JTAG TAP Options Sample MHS file entry for the combined JTAG chain Connects the PowerPC  JTAG TAP into the FPGA dedicated JTAG chain after configuration

Hardware Design - 3 - 62 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Virtex-II Pro Split JTAG Chains User-defined JTAG pins – Provides a direct and isolated connection to the PPC405 JTAG I/F – JTAGPPC block is not used in this configuration – The isolated chain supports embedded development and debug tools TDO TDI PPC 405 User-Defined JTAG Pins on the FPGA Fixed/Dedicated JTAG Pins on the FPGA CPU JTAG DEBUG PORT FPGA JTAG CONFIG PORT

Hardware Design - 3 - 63 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Virtex-II Pro Combined JTAG Chains Using the JTAGPPC block – Integrates the PPC405 with the FPGA fabric JTAG chain (dedicated JTAG pins) – The combined chain supports development and debug tools ChipScope  Pro (PC4) iMPACT  (PC4) GDB (PC4) SingleStep  XE (visionPROBEII  ) PPC 405 User-Defined JTAG Pins on the FPGA Fixed/Dedicated JTAG Pins on the FPGA CPU JTAG DEBUG PORT FPGA JTAG CONFIG PORT TDO TDI JTAG PPC

Hardware Design - 3 - 64 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Virtex-II Pro Combined JTAG Chains If the JTAG PPC controller is used to connect the PowerPC  405 CPU into a combined JTAG chain with the FPGA, then all PowerPC 405 cores are connected in for multi-CPU Virtex-II Pro  versions

Hardware Design - 3 - 65 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only FPGA JTAG Chain Summary TCK, TMS, TDI, and TDO wires of the PowerPC  405 CPU hard core are soft connections The Virtex-II Pro  IR register length is six, plus four per CPU – 10 for the single CPU — i.e., 2VP4/7 – 14 for dual CPU — i.e., the 2VP20/30/40/50/70/100 – 22 for quad CPU — i.e., the 2VP125 The instruction register length must be maintained before and after configuration of the FPGA An EXTRA register compensates for the missing CPU IR register before configuration, and after configuration when the CPU JTAG is on I/O pins (i.e., JTAGPPC Bbock is used)

Hardware Design - 3 - 69 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only JTAG Configuration/Wakeup with Combined JTAG Chains Combined JTAG chain designs allow configuration of FPGA, CPU, and external memory all at once Via JTAG, system configuration can take place as follows: – Configure the FPGA – Wait until the FPGA comes out of configuration mode – Configure the CPU, CPU caches, OCM, and any external memory that is accessible by the CPU – Set the PC to the start address of the code – Execute the code JTAG commands can exist as SVF in configuration memory

Hardware Design - 3 - 71 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Review Questions What connections must be made to debug software on the IBM PowerPC  processor? Where do the following vectors reside in the MicroBlaze  processor? – Reset – Interrupt – Exception What is the starting address of the code when LMB memory is present? Where does the reset vector reside in the PowerPC processor?

Hardware Design - 3 - 72 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Answers What connections must be made in to debug software on the IBM PowerPC  processor? – PowerPC JTAG ports connecting either the JTAGPPC component or the external pins Where do the following vectors reside in the MicroBlaze  processor? – Reset (0x00000000) – Interrupt (0x00000010) – Exception (0x00000008) What is the starting address of the code if LMB memory is present? – 0x00000018 Where does the reset vector reside in the PowerPC processor? – 0xFFFFFFFC

Hardware Design - 3 - 73 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Where Can I Learn More? Tool documentation – Processor IP Reference Guide Processor documentation – PowerPC Processor Reference Guide – PowerPC 405 Processor Block Reference Guide – MicroBlaze Processor Reference Guide Support website – EDK Home Page: support.xilinx.com/edk

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© 2004 Xilinx, Inc. All Rights Reserved Hardware Design.

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