1. Electrical Characteristics of ICs Part 3 Last Mod: January 2008  Paul R. Godin

2. Input/Output Voltages Elec3.2

3. Voltage and Logic Values Digital logic is represented as a voltage value. We are accustomed to assuming the following: –Logic high = 5V –Logic Low = 0V In reality: –Applied voltage values, and the resultant logic highs and lows, vary by device family. Some logic operates on 3.3 Volts, others on 12 Volts and yet other applications operate on a +12/-12 Volt logic. –many digital logic devices produce logic values that are not ideal. Elec3.3

4. Voltage Issues When designing systems, we must ensure that the logic voltage output of a (driving) gate will be interpreted properly by the receiving (loading) gate. Elec3.4 Vcc 1 Vcc 2

5. Output Voltage Specifications V OH : Voltage Output High. –Minimum voltage produced for a high state. V OL : Voltage Output Low. –Maximum voltage produced for a low state. Output Voltage Minimum Maximum V OH V OL Some TTL logic high outputs can be as little as 2.4 volts (on a 5 Volt system). Elec3.5

6. Input Voltage Specifications V IH : Voltage Input High. –Minimum voltage required for a high state. V IL : Voltage Input Low. –Maximum voltage required for a low state. Minimum Maximum V IH V IL Elec3.6 Input Voltage

7. Voltage Output/Input V OH V OL V IH V IL Undefined V CC Ground Undefined OutputInput Minimum Maximum Gate inputs that receive voltage levels within the undefined zone are unable to reliably determine the logic level. Elec3.7

8. IC’s must have minimum and maximum criteria for output levels. –For output, the high must have a minimum acceptable voltage level –For output, the low must have a maximum acceptable voltage level IC’s must have minimum and maximum criteria for input levels –For input, the high must have a minimum acceptable voltage level –For input, the low must have a maximum acceptable voltage level Voltage Characteristics Elec3.8

9. Noise Margin Elec3.9

10. Noise Noise: Unwanted electrical signal. Noise Margin: The ability to tolerate noise. –Noise margin defines the difference between the worst- case voltage output and input levels. CMOS devices have larger input logic level ranges, making them less susceptible to noise. Elec3.10

11. Voltage Output/Input OutputInput V OH V OL V IH V IL Undefined V CC Ground Undefined Minimum Maximum Noise Margin Elec3.11

12. Noise Anticipated Signal Actual Signal with Noise Undefined Output Elec3.12 LOW HIGH Undefined LOW HIGH Undefined Input

13. Improved Noise Margin Anticipated Signal Actual Signal with Noise Output Elec3.13 LOW HIGH Undefined LOW HIGH Undefined Input

14. Noise Margin Calculation Noise Margin is the difference between the worst-case output voltages to the worst-case input levels. Elec3.14

15. Noise Margin Example 4011B: –V OH : 4.95 V –V OL : 0.05 V –V IH : 3.5 V –V IL : 1.5 V OutputInput Minimum Maximum 4.95 V 0.05 V 3.5 V 1.5 V Noise Margin Elec3.15

16. Noise Margin Example 7400: –V OH : 2.4 V –V OL : 0.4 V –V IH : 2 V –V IL : 0.8 V OutputInput Minimum Maximum 2.4 V 0.4 V 2 V 0.8 V Noise Margin Elec3.16

17. END ©Paul R. Godin prgodin @ gmail.com Elec3.17