1. Physical Limits of Computing Dr. Mike Frank CIS 6930, Sec. #3753X Spring 2002 Lecture #23 Adiabatic Electronics & CMOS Mon., Mar. 11

2. Administrivia & Overview Don’t forget to keep up with homework!Don’t forget to keep up with homework! –We are  7 out of 14 weeks into the course. You should have earned  ~50 points by now.You should have earned  ~50 points by now. Course outline:Course outline: –Part I&II, Background, Fundamental Limits - done –Part III, Future of Semiconductor Technology - done –Part IV, Potential Future Computing Technologies - done –Part V, Classical Reversible Computing Fundamentals of Adiabatic Processes & logic - last Wed. & Fri. (----------------------- Spring Break ------------------------)Fundamentals of Adiabatic Processes & logic - last Wed. & Fri. (----------------------- Spring Break ------------------------) Adiabatic electronics & CMOS logic families - TODAYAdiabatic electronics & CMOS logic families - TODAY Limits of adiabatics: Leakage and clock/power supplies. - Wed. 3/13Limits of adiabatics: Leakage and clock/power supplies. - Wed. 3/13 RevComp theory I: Emulating Irreversible Machines - Fri. 3/15RevComp theory I: Emulating Irreversible Machines - Fri. 3/15 RevComp theory II: Bounds on Space-Time Overheads - Mon. 3/18RevComp theory II: Bounds on Space-Time Overheads - Mon. 3/18 (plus ~7 more lectures…)(plus ~7 more lectures…) –Part VI, Quantum Computing –Part VII, Cosmological Limits, Wrap-Up

3. Adiabatic electronics & CMOS implementations

4. Conventional Gates are Irreversible Logic gate behavior (on receiving new input):Logic gate behavior (on receiving new input): –Many-to-one transformation of local state! –Required to dissipate bT by Landauer principle –Incurs ½CV 2 dissipation in 2 out of 4 cases. inout Example: Static CMOS Inverter: Transformation of local state:

7. Exact formula: for frequency reduction f :  RC/t

9. Adiabatic Rules for Transistors Rule 1: Never turn on a transistor if it has a nonzero voltage across it!Rule 1: Never turn on a transistor if it has a nonzero voltage across it! –I.e., between its source & drain terminals. –Why: This erases info. & causes ½CV 2 disspation. Rule 2: Never apply a nonzero voltage across a transistor even during any on  off transition!Rule 2: Never apply a nonzero voltage across a transistor even during any on  off transition! –Why: When partially turned on, the transistor has relatively low R, gets high P=V 2 /R dissipation. –Corollary: Never turn off a transistor if it has a nonzero current going through it! Why: As R gradually increases, the V=IR voltage drop will build, and then rule 2 will be violated.Why: As R gradually increases, the V=IR voltage drop will build, and then rule 2 will be violated.

10. Adiabatic Rules continued Transistor Rule 3: Never suddenly change the voltage applied across any on transistor.Transistor Rule 3: Never suddenly change the voltage applied across any on transistor. –Why: So transition will be more reversible; dissipation will approach CV 2 (RC/t), not ½CV 2. Adiabatic rules for other components: Diodes: Don’t use them at all!Diodes: Don’t use them at all! –There is always a built-in voltage drop across them! Resistors: Avoid moderate network resistances.Resistors: Avoid moderate network resistances. –e.g. stay away from range >10 k  and 10 k  and <1 M  Capacitors: Minimize, reliability permitting.Capacitors: Minimize, reliability permitting. –Note: Dissipation scales with C 2 !

11. Transistor Rules Summarized off high on highlow off high off low on high on low Legal transitions in green. (For n- or p-FETs.) Dissipative states and transitions in red. off highlow on highlow

12. Transformation of local state: 

13. Input-Barrier, Clocked-Bias Retractile Cycle of operation:Cycle of operation: –Inputs raise or lower barriers Do logic w. series/parallel barriersDo logic w. series/parallel barriers –Clock applies bias force which changes state, or not 0 0 0 1 0 N * Must reset output prior to input. * Combinational logic only! Input barrier height Clocked force applied  Examples: Hall’s logic, SCRL gates, Rod logic interlocks

15. Retractile Logic w. SCRL gates Simple combinational logic of any depth N:Simple combinational logic of any depth N: –Requires N timing phases –Non-pipelined –No sequential reuse of HW (even worse) Sequential logic is required!Sequential logic is required! Time 

16. Sequential Retractile Logic Approach #1 (Hall ‘92):Approach #1 (Hall ‘92): –After every N stages, invoke an irreversible latch stores the output of the last stagestores the output of the last stage –Then, retract all the stages, –and begin a new cycle Problems:Problems: –Reduces dissipation by at most a factor of N –Also reduces HW efficiency by order N! In worst case, compared to a pipelined, sequential circuitIn worst case, compared to a pipelined, sequential circuit Approach #2 (Knight & Younis, ‘93):Approach #2 (Knight & Younis, ‘93): –The “store output” stage can also be reversible! –Gives fully-adiabatic, sequential, pipelined circuits! N can be as small 1 or 2 & still have arbitrarily high QN can be as small 1 or 2 & still have arbitrarily high Q

17. Simple Reversible CMOS Latch Uses a standard CMOS transmission gateUses a standard CMOS transmission gate Sequence of operation:Sequence of operation: (1) input initially matches latch contents (output) (2) input changes  output changes (3) latch closes (4) input removed P P inout BeforeInputInput input:arrived:removed: inoutinoutinout aaaaaa bbab

18. Resetting a Reversible Latch Can reversibly unlatch data as follows: (exactly the reverse of the latching process)Can reversibly unlatch data as follows: (exactly the reverse of the latching process) –(1) Data value d stored on memory node M. –(2) Present an exact copy of d on input. –(3) Open the latch (connecting input to M). No dissipation since voltage levels matchNo dissipation since voltage levels match –(4) Retract the copy of d from the input. Retracts copy stored in latch also.Retracts copy stored in latch also.

19. Input-Bias Clocked-Barrier Logic Cycle of operation:Cycle of operation: –Data input applies bias Add forces to do logicAdd forces to do logic –Clock signal raises barrier –Data input bias removed 0 0 1 1 1 0 N Input “0” Input “1” Retract input Clock barrier up Clock up Can amplify/restore input signal in clocking step. Can reset latch reversibly given copy of contents. Examples: Adiabatic QDCA, SCRL latch, Rod logic latch, PQ logic, Buckled logic

22. SCRL 6-tick clock cycle in out Initial state: All gates off, all nodes neutral.

23. SCRL 6-tick clock cycle in out Tick #1: Input goes valid, forward T-gate opens.

24. SCRL 6-tick clock cycle in out Tick #2: Forward gate charges, output goes valid. (Tick #1 of subsequent gate.)

25. SCRL 6-tick clock cycle in out Tick #3: Forward T-gate closes, reverse gate charges.

26. SCRL 6-tick clock cycle in out Tick #4: Reverse T-gate opens, forward gate discharges.

27. SCRL 6-tick clock cycle in out Tick #5: Reverse gate discharges, input goes neutral.

28. SCRL 6-tick clock cycle in out Tick #6: Reverse T-gate closes, output goes neutral. Ready for next input!

29. 24 ticks/cycle in this version- includes 2-level retractile stages

32. Some Interesting Questions About pipelined, sequential, fully-adiabatic CMOS logic:About pipelined, sequential, fully-adiabatic CMOS logic: –Q: Does it require these intermediate voltage levels? A: No, you can get by with only 2 different levels.A: No, you can get by with only 2 different levels. –Q: What is the minimum number of externally provided timing signals you can get away with? A:  4 (  12 if split levels are used)A:  4 (  12 if split levels are used) –Q: Can the order-N different timing signals needed for long retractile cascades be internally generated within an adiabatic circuit? A: Yes, but not statically, unless N 2 hardware is usedA: Yes, but not statically, unless N 2 hardware is used –where N is the number of stages per full sequential cycle We now demonstrate these answers.We now demonstrate these answers.

33. 2LAL: 2-level Adiabatic Logic Use simplified T-gate symbol:Use simplified T-gate symbol: Basic buffer element:Basic buffer element: –cross-coupled T-gates Only 4 timing signals, 4 ticks per cycle:Only 4 timing signals, 4 ticks per cycle: –  i rises during tick i –  i falls during tick ((i+1) mod 4)+1 P P P :: in out 22 11 1 2 3 4 Tick # 11 22 33 44

34. 2LAL Cycle of Operation in in  1 in=0 1111 1111 2020 2121 out  1 out=0 1010 1010 in  0 2121 out  0

35. Shift Register Structure 1-tick delay per logic stage:1-tick delay per logic stage: Logic pulse timing & propagation:Logic pulse timing & propagation: in 22 11 33 22 44 33 out 11 44 in 1 2 3 4...

36. More complex logic functions Non-inverting Boolean functions:Non-inverting Boolean functions: For inverting functions, must use quad-rail logic encoding:For inverting functions, must use quad-rail logic encoding: –To invert, just swap the rails! Zero-transistor “inverters.”Zero-transistor “inverters.” A B  A ABAB A B  ABAB A0A0 A0A0 A1A1 A1A1 A = 0A = 1

37. Hardware Efficiency issues Hardware efficiency: How many logic operations per unit hardware per unit time?Hardware efficiency: How many logic operations per unit hardware per unit time? Hardware spacetime complexity: How much hardware for how much time per logic op?Hardware spacetime complexity: How much hardware for how much time per logic op? We’re interested in minimizing: (# of transistors) × (# of ticks) / (gate cycle)We’re interested in minimizing: (# of transistors) × (# of ticks) / (gate cycle) SCRL inverter, w. return path:SCRL inverter, w. return path: –(8 transistors)  (6 ticks) = 48 transistor-ticks Quad-rail 2LAL buffer stage:Quad-rail 2LAL buffer stage: –(16 transistors)  (4 ticks) = 64 transistor-ticks

38. More SCRL vs. 2LAL SCRL reversible NAND, w. all inverters:SCRL reversible NAND, w. all inverters: –(23 transistors)  (6 ticks) = 138 T-ticks Quad-rail 2LAL AND:Quad-rail 2LAL AND: –(48 transistors)  (4 ticks) = 192 T-ticks Result of comparison: Although 2LAL minimizes # of rails, and # ticks/cycle, it does not minimize overall spacetime complexity.Result of comparison: Although 2LAL minimizes # of rails, and # ticks/cycle, it does not minimize overall spacetime complexity. The question of whether 6-tick SCRL minimizes per-op spacetime complexity among pipelined adiabatic CMOS logics is still open.The question of whether 6-tick SCRL minimizes per-op spacetime complexity among pipelined adiabatic CMOS logics is still open.