1. VLSI Design & Embedded Systems Conference January 2015 Bengaluru, India Few Good Frequencies for Power-Constrained Test Sindhu Gunasekar and Vishwani D. Agrawal

2. Test Power VLSI system-on-chip devices contain scan based test structures. Scan tests use large number of clock cycles. Few test cycles consume two to four times the functional mode power. Such test cycles enforce a slow test clock. Long test times increase manufacturing cost. 2/3/2016© VLSI Design & Embedded Systems Conference - 20152

3. Background on Test Power 2/3/2016© VLSI Design & Embedded Systems Conference - 20153 Dynamic current I i (t) and cycle power P i in test mode. If functional clock of period T were to be used, cycle power exceeds P max due to high circuit activity. Hence, a slower clock T’ is used for testing.

4. Background on Multifrequency (Aperiodic) Testing 2/3/2016© VLSI Design & Embedded Systems Conference - 20154 In an aperiodic test, to reduce test time each test cycle uses customized shortest possible period such that the cycle power does not exceed P max. Reference: P. Venkataramani and V. D. Agrawal, “ATE Test Time Reduction Using Asynchronous Clocking,” in Proc. International Test Conf., Sept. 2013. Paper 15.3.

5. Test Time Test time (TT) = E total /P av Power constrain, P av ≤ P max Conventional synchronous test (N clock cycles) TT = N E max /P max Aperiodic test (N clock cycles) TT = ∑ N E i /P max = E total /P max 2/3/2016© VLSI Design & Embedded Systems Conference - 20155

6. Advantest T2000GS ATE Used to test integrated circuits for faults after fabrication. Provides test patterns and clock to test the device under test (DUT). Performs measurements and evaluates the test results. 2/3/2016© VLSI Design & Embedded Systems Conference - 20156

7. Testing Costs ATE has high initial and recurring costs. The testing cost of using an ATE increases directly with the time spent on testing the DUT. Adds to the final cost of the chip. As chip complexity increases, it costs more to test a transistor than to manufacture it. Reducing test time reduces cost of chip. 2/3/2016© VLSI Design & Embedded Systems Conference - 20157

8. Problem of Finding Few Good Clock Frequencies Number of clocks k ranges from 1 to N. k = 1 is synchronous test. For given k and N, we must find k clock periods that minimize the test time TT(k). TT sync ≥ TT(k) ≥ TT aper 2/3/2016© VLSI Design & Embedded Systems Conference - 20158

9. Constraints for Frequencies 2/3/2016© VLSI Design & Embedded Systems Conference - 20159

10. ISCAS'89 Benchmark s1238 3,361 cycle scan test P max = 2.52mW T min = 2.11ns Structure constrained cycles: E j < P max x T min = 0.0053nJ shown in red 2/3/2016© VLSI Design & Embedded Systems Conference - 201510

11. Sorted Energy Profile 2/3/2016© VLSI Design & Embedded Systems Conference - 201511

12. The Maximum Power Algorithm 2/3/2016© VLSI Design & Embedded Systems Conference - 201512 E 1 = E max is the maximum energy cycle E N = s x E max is the minimum energy cycle ; s ≤ 1 E N = E min = E max

13. Power Profile for Four Clocks 2/3/2016© VLSI Design & Embedded Systems Conference - 201513 Sorted test clock cycles, i N (P max ) Normalized Power T 1 = E max /P max T 2 = r 1 T 1 T 3 = r 1 r 2 T 1 T 4 = r 1 r 2 r 3 T 1 1.0 Average power r1r1 r3r3 r4r4 r2r2

14. Idea of kth-Root Algorithm 2/3/2016© VLSI Design & Embedded Systems Conference - 201514 Sorted test clock cycles, i N (P max ) Normalized Power T 1 = E max /P max T 2 = r T 1 T 3 = r 2 T 1 T 4 = r 3 T 1 1.0 Average power r = r 1 = r 2 = r 3 = r 4 = s 1/4, s = E min /E max r r r r

15. k-th Root Solution 2/3/2016© VLSI Design & Embedded Systems Conference - 201515

16. Locally Exhaustive Search For large values of k, typically k ≥ 10, the piecewise linear approximation gives reasonable accuracy to kth-root algorithm. For small k a locally exhaustive search (LES) can find an optimum solution. LES is significantly more efficient than directed search or simulated annealing. LES iteratively improves the kth-root solution of k clock periods T 1 through T k. 2/3/2016© VLSI Design & Embedded Systems Conference - 201516

17. Test Time for s1238 with k Clocks Test time for s1238 with k clocks. Clock periods were first obtained by the kth-root algorithm and then refined by locally exhaustive search (LES). 2/3/2016© VLSI Design & Embedded Systems Conference - 201517

18. CPU Time 2/3/2016© VLSI Design & Embedded Systems Conference - 201518 CPU time on Intel Core i3 CPU, 2.27GHz 4GB RAM for kth-root and LES solutions for s1238 circuit. Total test clock cycles, N = 3,361

19. Test Times for ISCAS’89 Benchmark Circuits © VLSI Design & Embedded Systems Conference - 201519 Test times with clocks obtained from k-th root and LES optimization for ISCAS’89 Benchmark Circuits.

20. Conclusion Almost all the possible test time saving is achieved by just four to ten selected clocks. The kth-root solution, although extremely simple, is accurate for ten or more clocks. For fewer clocks the locally exhaustive search (LES) algorithm provides an effective solution. 2/3/2016© VLSI Design & Embedded Systems Conference - 201520