1. CEC 220 Digital Circuit Design Mealy and Moore State Machines Friday, March 27 CEC 220 Digital Circuit Design Slide 1 of 16

2. Lecture Outline Friday, March 27 CEC 220 Digital Circuit Design Design of a Sequence Detector Guidelines for Construction of State Graphs Slide 2 of 16

3. Mealy and Moore State Machines Design of a Sequence Detector Friday, March 27 CEC 220 Digital Circuit Design Design a “state machine” to detect two or more 1’s in a row on a clocked input  A sequence detector  Assert the output ‘Z’ if correct sequence is detected …,0,1,1,0,0,… State Machine w z Clk Slide 3 of 16

4. Mealy and Moore State Machines Design of a Sequence Detector Friday, March 27 CEC 220 Digital Circuit Design Design a “state machine” to detect two or more 1’s in a row on a clocked input S0 z=0 S1 z=0 S11 z=1 RESET w=1 w=0 w=1 w=0 State Name Output Legend: State Transitions ONLY occur when the clock “ticks” Input = ? Slide 4 of 16

5. Mealy and Moore State Machines Design of a Sequence Detector – Moore Design Friday, March 27 CEC 220 Digital Circuit Design State Transition Table Present State Next StatePresent Output (Z) w=0w=1 S00 S1 0S0S11 1S0S11 Present State Next StatePresent Output (Z) w=0w=1 00 01 10 11 Present State Next StatePresent Output (Z) w=0w=1 00 01 0 0010 0 0010 1 11 XX X QAQBQAQB S0 =00 S1 =01 S11 =10 State Encodings How many FFs will we need? Slide 5 of 16

6. 01 0 1 Mealy and Moore State Machines Design of a Sequence Detector – Moore Design Friday, March 27 CEC 220 Digital Circuit Design Circuit Design  Let’s use D-type FFs 01 00 01 11 10 01 00 01 11 10 01 0000 0101 11XX 1001 01 0001 0100 11XX 1000 01 001 10X Slide 6 of 16

7. Mealy and Moore State Machines Design of a Sequence Detector – Moore Design Friday, March 27 CEC 220 Digital Circuit Design Circuit Design Clk w Z Input Logic Flip-Flops Output Logic Output is a function of ONLY the current state Slide 7 of 16

8. Mealy and Moore State Machines Design of a Sequence Detector – Moore Design Friday, March 27 CEC 220 Digital Circuit Design Architecture of a Moore State Machine  Outputs are a function of only the current state Flip-Flops Q’s Clock FF Inputs Input Combinational Logic State of FFs Inputs Output Combinational Logic Outputs Slide 8 of 16

9. Mealy and Moore State Machines Design of a Sequence Detector – Mealy Design Friday, March 27 CEC 220 Digital Circuit Design Design a “state machine” to detect two or more 1’s in a row on a clocked input  Now we will allow the state machine’s output to change asynchronously!! o i.e., NOT synchronized with the clock S0S1 RESET w=0 / z=0 w=1 / z=0 w=0 / z=0 w=1 / z=1 State Name Legend: State Transitions ONLY occur when the clock “ticks” Input = ? / Output = ? Slide 9 of 16

10. Mealy and Moore State Machines Design of a Sequence Detector – Mealy Design Friday, March 27 CEC 220 Digital Circuit Design State Transition Table QAQA S0 =0 S1 =1 State Encodings How many FFs will we need? Present State Next StatePresent Output (Z) w=0w=1w=0w=1 S0 00 S1 S001 S1 Present State Next StatePresent Output (Z) w=0w=1w=0w=1 000 101 Present State Next StatePresent Output (Z) w=0w=1w=0w=1 00100 10101 Slide 10 of 16

11. Mealy and Moore State Machines Design of a Sequence Detector – Mealy Design Friday, March 27 CEC 220 Digital Circuit Design Circuit Design  Let’s use D-type FFs Present State Next StatePresent Output (Z) w=0w=1w=0w=1 00100 10101 01 0 1 01 001 101 01 0 1 01 000 101 Slide 11 of 16

12. Mealy and Moore State Machines Design of a Sequence Detector – Mealy Design Friday, March 27 CEC 220 Digital Circuit Design Circuit Design Clk w Input Logic Flip-Flops Output Logic Z Output is a function of the current state and the input Output no longer synchronized with the clock Slide 12 of 16

13. Mealy and Moore State Machines Design of a Sequence Detector – Mealy Design Friday, March 27 CEC 220 Digital Circuit Design Architecture of a Mealy State Machine  Outputs are now a function of the current state and the input Flip-Flops Q’s Clock FF Inputs Input Combinational Logic State of FFs Inputs Output Combinational Logic Outputs Slide 13 of 16

14. Mealy and Moore State Machines Design of a Sequence Detector Friday, March 27 CEC 220 Digital Circuit Design Comparing the Mealy and Moore Designs Moore State Machine Mealy State Machine 0 10110 Slide 14 of 16 ???

15. Friday, March 27 CEC 220 Digital Circuit Design Comparing Mealy and Moore State Machines Moore State MachineMealy State Machine States change on the clock edge Output is only a function of the current state Output changes are synchronized with the clock Typically, more states than a Mealy machine States change on the clock edge Output is a function of the current state and the current input Output changes are NOT synchronized with the clock Typically, fewer states than a Moore machine Mealy machines can produce false outputs Mealy machines outputs are only valid immediately preceding clock edges!! Slide 15 of 16

16. Next Lecture Friday, March 27 CEC 220 Digital Circuit Design Analysis from Timing Diagrams  Reverse engineering Analysis from Circuit Diagrams  Reverse engineering Slide 16 of 16