1. LHC Electronics Workshop, Amsterdam, 20031 The MGPA ECAL readout chip for CMS Mark Raymond, Geoff Hall, Imperial College London, UK. Jamie Crooks, Marcus French, Rutherford Appleton Laboratory, UK. OUTLINE Introduction Design Measured Performance Conclusions 9 th Workshop on Electronics for LHC Experiments, Amsterdam, 2003 Multi–Gain Pre-Amplifier - 0.25  m CMOS chip for CMS ECAL

2. LHC Electronics Workshop, Amsterdam, 20032 New CMS VFE (Very Front End) architecture 1 6 12 MGPA 12 bits 2 bits LOGIC Multi-channel ADC opto-electric barrel: APD endcap: VPT CMS ECAL Lead Tungstate crystal calorimeter with APD/VPT readout for barrel/endcap General approach use multiple gain ranges -> high resolution with only 12 bit ADC only transmit value for highest gain channel-in-range => have to take decision on front end Previous architecture range decision taken in preamplifier (complex chip), followed by single channel commercial ADC New architecture 3 parallel gain channels (MGPA), multi-channel ADC, range decision taken by logic in ADC chip use 0.25  m CMOS to take advantage of: radiation hardness system simplifications: single 2.5V supply, power savings short production turnaround, high yield, cheaper Short timescale for development design begun mid 2002, submission early 2003, die received May 2003, packaged die since August

3. LHC Electronics Workshop, Amsterdam, 20033 MGPA Target Specifications ParameterBarrelEnd-Cap fullscale signal60 pC16 pC noise level10,000e (1.6 fC)3,500e (0.56 fC) input capacitance~ 200 pF~ 50 pF output signals (to match ADC) differential 1.8 V, +/- 0.45 V around Vcm = (Vdd-Vss)/2 = 1.25 V gain ranges1, 6, 12 gain tolerance (each range) +/- 10 % linearity (each range) +/- 0.1 % fullscale pulse shaping40 nsec CR-RC pulse shape matching (Vpk-25)/Vpk < 1 % within and across gain ranges Barrel/Endcap read out using APD/VPT different capacitance and photoelectric conversion factors spec. review -> 3 gain ranges sufficient to deliver required performance -> MGPA design easier Additional calibrate feature -> not precision but allows charge injection to each front end chip Vpk-25Vpk

4. LHC Electronics Workshop, Amsterdam, 20034 MGPA Architecture RFRF charge amp. R G1 diff. O/P stages CFCF V CM CICI RIRI gain stages RIRI DAC I 2 C and offset generator ext. trig. 1 st stage R F C F = 40 nsec. (avoids pile-up) choose R F C F for barrel/endcap external components => 1 chip suits both 3 gain channels 1:6:12 set by resistors (on-chip) for linearity differential current O/P stages external termination 2R I C I = 40 nsec. => low pass filtering on all noise sources within chip calibration facility prog. amplitude needs ext. trigger I 2 C interface to programme: output pedestal levels enable calibration feature cal DAC setting C CAL R G2 R G3 I/P V CM CICI RIRI RIRI CICI RIRI RIRI RFCFRFCF i i i

5. LHC Electronics Workshop, Amsterdam, 20035 Noise Sources C IN v FET 2 v Rpf 2 R pf charge amp. s.f. RGRG diff. O/P gain stage C pf V CM CICI RIRI transconductance gain stage i CGFET 2 i RG 2 1 st stage Rpf dominates: 4900 electrons (barrel: Cpf//Rpf = 33 pF//1k2), 2700 (endcap: Cpf//Rpf = 8p2//4k7) I/P FET: W/L = 30,000/0.36, gm ~ 0.3 A/V -> 1800 electrons (barrel, 200pF), 660 (endcap, 50pF) => no strong dependence of overall noise on CIN gain stages high and mid gain ranges, R G low (few 10’s  additional noise small low gain range, R G (240  and CG FET noise dominate and spec. exceeded (factor ~3) but lowest gain range used for biggest signals => electronic noise contribution to overall energy resolution very small (for this range)

6. LHC Electronics Workshop, Amsterdam, 20036 Chip Layout I2C 1 st stage high gain stage diff. O/P stage offset gen. layout issues gain channels segregated as much as poss. with separate power pads -> try to avoid inter-channel coupling lots of multiple power pads die size ~ 4mm x 4mm packaged in 100 pin TQFP (14mm x 14mm) mid gain stage low gain stage diff. O/P stage

7. LHC Electronics Workshop, Amsterdam, 20037 Test Setup Pulse Gen. MGPA test board Programmable Attenuator True rms milli-voltmeter Scope diff. probe early tests used bare die – packaged chips only available more recently priority given to measurements for barrel gain (60 pC fullscale)

8. LHC Electronics Workshop, Amsterdam, 20038 Pulse Shape Measurements Volts time [nsec] low gain rangemid gain rangehigh gain range O/P signals probed individually 0 – 60 pC, 40 steps saturation in mid and high gain ranges no clamping outside linear range

9. LHC Electronics Workshop, Amsterdam, 20039 Differential Pulse Shape Measurements Volts time [nsec] low gain rangemid gain rangehigh gain range differential O/P signals (diff. probe) 0 – 60 pC, 40 steps no obvious signs of distortion in lower gain ranges => effective gain channel segregation in layout gain ratios 1 : 5.6 : 11.3 (c.f. 1 : 6 : 12) linear range

10. LHC Electronics Workshop, Amsterdam, 200310 Linearity: High Gain Channel spec. linearity [% fullscale] Linearity [% fullscale] = peak pulse ht. – fit (to pk pulse ht) X100 fullscale signal relative signal size linearity within (or close to) spec for a range of gain stage bias currents => not v. sensitive to bias conditions 5.4 pC

11. LHC Electronics Workshop, Amsterdam, 200311 Linearity: Mid and Low gain channels spec. linearity [% fullscale] relative signal size midlow similar picture to high gain channel 11 pC60 pC

12. LHC Electronics Workshop, Amsterdam, 200312 Pulse Shape Matching normalise to max pulse ht. pulse shape matching important within and across gain ranges to quantify use pulse shape matching factor, PSMF = Vpk-25 Vpk Vpk-25 pulse shapes for all 3 gain ranges (11 steps / range) all 33 pulse shapes overlaid pulse height [Volts] time [nsec.]

13. LHC Electronics Workshop, Amsterdam, 200313 Pulse Shape Matching spec. Pulse shape matching [%] = (PSMF – Average PSMF) x 100 Average PSMF (Average PSMF = average over all pulse shapes and all 3 gain ranges) relative signal size [1=fullscale] pulse shape matching [%] pulse shape matching close to spec. (+/- 1%)

14. LHC Electronics Workshop, Amsterdam, 200314 Noise Barrel (33 pF // 1.2k) Cstray (~20 pF) Cstray + 180 pF simulation 200 pF high7,0007,8506,200 mid8,2509,1008,200 low~ 28,000 35,400 use wide bandwidth true rms meter (single ended I/P) => need diff. to singled ended buffer circuitry (adds some extra filtering) => extra buffer noise contribution to subtract weak dependence on input capacitance as expected estimated errors: ~ 10% high and mid-gain ranges, ~ 20% low gain range (buffer circuitry dominates here) Endcap (8.2 pF // 4k7) Cstray (~20 pF) Cstray + 56 pF simulation 50 pF 2,9003,0502,700 3,3003,4503,073 ~ 8,500 9,800 within spec. < 10,000 (barrel) < 3,500 (endcap) electronic noise not significant for low gain range

15. LHC Electronics Workshop, Amsterdam, 200315 Radiation Tests 10 keV X-rays (spectrum peak), dosimetry accurate to ~ 10%, doserate ~ 1 Mrad/hour, no anneal ~ 3% reduction in gain after 5 Mrads (2 x worst case) no measurable effect on noise lowmidhigh pre-rad 5 Mrads

16. LHC Electronics Workshop, Amsterdam, 200316 I 2 C Pedestal Adjust Volts nsec. I2C=0 I2C=50 I2C=100 VCM ADC I/P range High gain range, ~ fullscale signal. I2C pedestal adjust sets offset current to diff O/P stage (one for each gain range) I2C ~ 50 about right in this case

17. LHC Electronics Workshop, Amsterdam, 200317 On-chip Calibration ext. 10pF MGPA I/P Volts nsec. simple DAC allows programmable (I 2 C) amplitude charge injection -> range of signal sizes for each gain range external trigger required allows functional verification during chip screening and in-system I2C external edge trigger

18. LHC Electronics Workshop, Amsterdam, 200318 Power, Yield, Things to fix Power consumption bias currents to all stages set by external resistors 240 mA drawn from 2.5 V rail => 600 mW (1 st stage: 150, gain stages: 300, diff. stages: 150) Yield appears very high, e.g. only one faulty chip found in basic tests on ~ 50 chips Things to fix/change high frequency instability around first stage ext. feedback components + packaging/PCB layout capacitance + bond inductance -> LC resonance can be made stable insert small series damping resistors and reduce bandwidth better fix? – needs more study add on-chip reference for offset bias generator modify default I 2 C settings I/P Vs

19. LHC Electronics Workshop, Amsterdam, 200319 Conclusions First iteration of MGPA successful Analogue performance good gain linearity pulse shape matching noise rad-hard as expected What next? Verify performance can be maintained in system in conjunction with APD (& VPT), ADC, rest of FE components - work already underway at CERN timescale short - next submission (engineering run) soon within (or v. close to) spec.

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