1. Field Programmable Port Extender (FPX) 1 Example RAD Design: IP Router using Fast IP Lookup

2. Field Programmable Port Extender (FPX) 2 Overview Design Overview –Top-level RAD Design –Fast IP Lookup Module –FIPL Control and FIPL Engine Architecture Design Flow (UNIX, Exemplar, Xilinx) FPX file tree FIPL Simulation Environment Exercise #1: RAD_FIPL Cell I/O simulation Exercise #2: Structural VHDL, Cell I/O simulation (Break for software exercise) Exercise #3: Cell I/O simulation with software output Behavioral VHDL Tips & Sources

3. Field Programmable Port Extender (FPX) 3 Design Overview SRAM 1 SRAM 2 IP Lookup Engine counter On-Chip Cell Store SRAM 1 Interface Control Cell Processor Packet Reassembler RAD FPGA NID FPGA Extract IP Headers Remap VCIs for IP packets LC SW Request Grant 0 1 0 00 0 0 0 11 1 11 1 1 1 1

4. Field Programmable Port Extender (FPX) 4 Top-level Design (RAD_FIPL) FIPL Module Infrastructure –(2) SRAM Interfaces –Reconfiguration Control –Control Cell Processor CCP FIPL Module RECONFIG_CNTL SRAM_INTERFACE RAD_FIPL

5. Field Programmable Port Extender (FPX) 5 Fast IP Lookup Module IP Wrapper –Implements module cell I/O interfaces, cell FIFO –Extracts destination IP addresses, writes to IP address FIFO in FIPL Control –Reads next-hop FIFO in FIPL Control, modifies VCI of outgoing IP packets –Passes other ATM traffic FIPL Control –Implements module control and SRAM interfaces –Performs longest-prefix match address lookups IP Wrapper FIPL Control SRAM Interface SOC DATA TCA SOC DATA TCA RESET_L, CLK ENABLE_L READY_L Request, Grant, R/W, Address, Data_in, Data_out

6. Field Programmable Port Extender (FPX) 6 FIPL Control & FIPL Engine Architecture FIPL Control –Input FIFO for 32-bit IPv4 destination addresses –Output FIFO for 16-bit next- hops –State-machine guarantees delivery of next-hops in order of address arrival –Instantiates 3 FIPL Engines Multiplexes incoming data and outgoing addresses based on known engine cycle time FIPL Engine –Implements Tree Bitmap algorithm for longest prefix matching –Flops incoming data, 3-cycle logic computation, flops next read address SRAM Address SRAM Data IP Dest. Address Next Hop C/L FIPL Engine C/L FIPL Engine C/L FIPL Engine FIPL Control

7. Field Programmable Port Extender (FPX) 7 Optimal Design Flow UNIX Solaris OS HDL Specification (xemacs VHDL, Mentor Graphics) –Enumerate constraints (conservative delay estimates) –Design hardware (block diagrams, RTL) –FSM synthesis (memory latencies, etc.) –Behavioral VHDL description Avoid procedures and functions Use processes with caution (don’t imply latches) Simulation (ModelSim) –Simulate module partitions separately Full testbenches unnecessary, simple stimulus files suffice –Simulate full module Testbench with file I/O recommended –Simulate top-level design with module/infrastructure Use “fake_nid” files to simulate cell I/O

8. Field Programmable Port Extender (FPX) 8 Optimal Design Flow (continued) Synthesis (Exemplar, Synplicity) –Spectrum scripts for simple designs –Leonardo GUI for complex designs, multi-cycle paths –Synplicity GUI (faster for most designs) FIPL design will be migrated to Synplicity soon Place & Route (Xilinx Alliance Series) –Constraint passing caveats Make sure constraints generated by synthesis tool are passed forward to PAR tool using constraint editor Timing constriants may need to be repeated in PAR –Physical Constraints Pin mappings contained in rad.ucf –Floorplanning Essential for half-chip designs, timing critical modules Backannotated Gate-level Simulation (ModelSim)

9. Field Programmable Port Extender (FPX) 9 FPX File Tree Provided directories in all CAPS –Distinguishes original (sub)directories from those added by Kits members Create subdirectory for new module designs under MODULES –Perform local simulation and synthesis Create subdirectory for new top-level builds under TOP –Instantiate modules and necessary infrastructure –Perform system-level simulation, top-level synthesis

10. Field Programmable Port Extender (FPX) 10 FIPL Simulation Environment CCP_CELLS Micron ZBT SRAM model Micron ZBT SRAM model FAKE_NID SW_OUT FAKE_NID SW_IN FAKE_NID LC_OUT FAKE_NID LC_IN TESTBENCH CCP_RESPONSE IP_CELLS IP_RESULTS CCP FIPL Module RECONFIG_CNTL SRAM_INTERFACE RAD_FIPL

11. Field Programmable Port Extender (FPX) 11 Exercise #1: RAD_FIPL Cell I/O Simulation Download tutorial files from FPX Workshop Agenda page –fipl_tutorial.tar.gz Open cygwin window Expand files –“gunzip fipl_tutorial.tar.Z” –“tar -xvf fipl_tutorial.tar” Navigate source tree –“cd FPX_ROOT/RAD”, “ls” –“cd MODULES/IP_LOOKUP_ENGINE”, “ls” –“cd vhdl” –“less fipl_module.vhd” –“cd fipl” –“less fipl.vhd” –“cd../../../../INFRASTRUCTURE”, “ls” –Look at any infrastructure modules that interest you

12. Field Programmable Port Extender (FPX) 12 Exercise #1: RAD_FIPL Cell I/O Simulation Go to top-level VHDL directory –“cd ~/FPX_ROOT/RAD/TOP/RAD_FIPL/vhdl” –“less rad_fipl.vhd” (top-level structural VHDL) –Observe module instantiation and “wiring” Component –Entity declaration for module Instance –Module instantiation Signal –Wire, connects ports of entities, single driver, single or multiple receivers –“less testbench_rad_fipl.vhd” (testbench, structural VHDL) Go to top-level simulation directory –“cd../sim” –“less Makefile”

13. Field Programmable Port Extender (FPX) 13 Exercise #1: RAD_FIPL Cell I/O Simulation Examine input test vectors –“less CCP_CELLS.DAT” Cells to build tree bitmap data structure in memory Wait states prevent CCP buffers from overflowing –“less IP_CELLS.DAT” IP Packet test vectors (only the destination address is important, these are not proper AAL5 frames) IP destination address located in 7 th word of ATM cell Test vectors arrive on VCI=0x003E –(3 cell packet, DA = 0x0ABAC000, NH = 0x3F) –(2 cell packet, DA = 0xDA800000, NH = 0x22) –(1 cell packet, DA = 0x0ABAA000, NH = 0x04) »For example: 10.186.160.0 should be sent out on VCI 0x0004 –(1 cell packet, DA = 0x80000000, NH = 0x06) –(Change incoming VCI to 0x0064) –(Repeat vectors)

14. Field Programmable Port Extender (FPX) 14 Exercise #1: RAD_FIPL Cell I/O Simulation For new simulation environments, use “make newsim” to create new work directory –This is already done for the tutorial directory Compile FIPL module, infrastructure modules, RAD_FIPL, fake_NIDs, and testbench –“make enchilada” Simulate testbench –“make sim” –Picosecond resolution is necessary in order to use Micron memory models (“-t ps” option is used for vsim) –In ModelSim command window type “do rad_stim” This stimulus file will open the appropriate view windows for the simulator and run the simulation for the correct amount of time –Output cell files will be generated (CCP_RESPONSE.DAT, IP_RESULTS.DAT)

15. Field Programmable Port Extender (FPX) 15 Exercise #1: RAD_FIPL Cell I/O Simulation Examine “CCP_RESPONSE.DAT” –Note that OpCodes have been incremented Examine “IP_RESULTS.DAT” –Check for VCI = Next Hop for the destination address –For example: VCI = 0x003F new_cell 000003F8 8C000000 54686520 71756963 6B206272 6F776E20 0ABAC000 6A756D70 6564206F 76657220 74686520 6C617A79 20646F67 2E0A0000 DA = 0x0ABAC00 10.186.160.0 (7 th word of ATM cell for AAL5 frames)

16. Field Programmable Port Extender (FPX) 16 Exercise #1: RAD_FIPL Cell I/O Simulation Caveats and “features” –Tri-state I/O buffer simulation models generate undefined outputs when the input is tri-stated Not an issue for physical system due to pull-ups in FPGA –Warnings in ModelSim command window regarding simultaneous read/write to memory ports CCP FIFO uses a custom FIFO to examine the first word at the head of the FIFO Warnings will be address by new cell FIFO, but simulation operations correctly

17. Field Programmable Port Extender (FPX) 17 Exercise #2: Structural VHDL, Cell I/O Sim Backup old top-level structural VHDL –“cp rad_fipl.vhd rad_fipl.vhd.OLD” Download “rad_fipl_shell.vhd” from FPX Workshop Agenda page to ~/FPX_ROOT/RAD/TOP/RAD_FIPL/vhdl/ –This is the same top-level (structural) VHDL file as before, but the FIPL module has been removed –“mv rad_fipl_shell.vhd rad_fipl.vhd” Redesign the IP Lookup Engine and insert it in the top- level file –Just kidding, but now that you are awake… Attain a copy of the FIPL module entity for declaration in the top-level –Navigate the directory tree to the “vhdl/” directory for FIPL –Open “fipl_module.vhd” and make a copy of the entity port declaration

18. Field Programmable Port Extender (FPX) 18 Exercise #2: Structural VHDL, Cell I/O Sim Return to the top-level vhdl directory Insert the FIPL Module in the top-level structural VHDL file –Open “rad_fipl.vhd” in a text editor –Paste a copy of the FIPL module entity into “rad_fipl.vhd” above the “component” declaration for the CCP –Modify the entity port declaration to the correct syntax for a structural component declaration If you do not know the correct syntax, use the component declarations for the CCP and RECONFIG_CNTL as guides If you are having problems, consult the old structural VHDL for guidance; BUT DON’T CHEAT! –Paste another copy of the FIPL module entity into “rad_fipl.vhd” above the CCP instance “CCP_MOD:ccp” –Leave this unmodified for now

19. Field Programmable Port Extender (FPX) 19 Exercise #2: Structural VHDL, Cell I/O Sim –Declare all necessary signals needed for fipl_module “wiring” in the region where other signals are declared Cell I/O interfaces SRAM interface Control interface Consult the old structural VHDL for help –Return to the unmodified entity port delclaration for the FIPL –Modify to the correct instance syntax and use signals to “wire up” the FIPL module FIPL cell input interface should be wired to “LC_NID” pad signals FIPL cell output interface should be wired to “LC_RAD” pad signals FIPL SRAM interface should be wired to unoccupied port (mod1) of SRAM1 interface Clk should be connected to RAD_CLK reset_l, enable_l, and ready_l should be wired to mod0 port of the Reconfiguration Control

20. Field Programmable Port Extender (FPX) 20 Exercise #2: Structural VHDL, Cell I/O Sim Recompile top-level and testbench files –“make top” No need to recompile FIPL module –If there are errors, correct them –Consult old structural VHDL file for assistance with unresolvable errors Close the simulator (if still open from Exercise #1) in order to clear memory contents from previous simulation Remove old simulation output files –“rm CCP_RESPONSE.DAT” –“rm IP_RESULTS.DAT” Simulate the design –“make sim” –In the ModelSim command window, type “do rad_stim” –Check output files for correct results

21. Field Programmable Port Extender (FPX) 21 Exercise #3: Cell I/O Sim with SW Output Backup old data structure input file –“mv CCP_CELLS.DAT CCP_CELLS.DAT.OLD” Create new data structure input file –“mv NEW_CCP_CELLS.DAT CCP_CELLS.DAT” Close simulator from previous runs to clear memory Rerun simulation –“make sim” –In ModelSim command window “do rad_stim”

22. Field Programmable Port Extender (FPX) 22 Exercise #3: Cell I/O Sim with SW Output Check “IP_RESULTS.DAT” for correct output All lookups should be identical with exception to address 10.186.160.0 which should now be on outgoing VCI = 0x004D VCI = 0x003F new_cell 000004D8 8C000000 54686520 71756963 6B206272 6F776E20 0ABAC000 6A756D70 6564206F 76657220 74686520 6C617A79 20646F67 2E0A0000 DA = 0x0ABAC00 10.186.160.0 (7 th word of ATM cell for AAL5 frames)

23. Field Programmable Port Extender (FPX) 23 Behavioral VHDL Tips & Sources Design first, design again, then code Code should directly correspond to physical hardware –Think in terms of describing flip-flops, logic, multiplexors NOT procedure and object calls Partition FSMs for simplicity –Process using case statement for next state assignment Take care to include all signals that you condition on in the sensitivity list of the process (otherwise you will imply asynchronous latches) –Flip-flop for assigning next state to state –State signal used in logic operations outside of the state transition process Lots of good sources for help and guidance –Books “VHDL Make Easy!” Pellerin & Taylor “VHDL Starter’s Guide” Yalamanchili –FPX Mailing list

24. Field Programmable Port Extender (FPX) 24 End of Presentation