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– 1 – CSCE 211H Fall 2015 Lec 11 Flip Flop Excitation Tables Topics Sequential Circuits SR Latch Clocked SR Master Slave Master Slave VHDL Readings: 5.4, 5.9, 5.10, 4.4 October 21, 2015 CSCE 211 Digital Design
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– 2 – CSCE 211H Fall 2015 Overview Last Time Sequential Circuits: Basic Nor LatchNew Sequential Circuits Clocked SR flip flops Master Slave SR VHDL – two bit adderArduino Kits http://www.arduino.cc/ ; http://arduino.cc/en/Guide/HomePage http://www.arduino.cc/ http://arduino.cc/en/Guide/HomePage
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– 3 – CSCE 211H Fall 2015 Register Bank - Mux – ALU - Decoder
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– 4 – CSCE 211H Fall 2015 Clocked SR-Latch http://www.play-hookey.com/digital/ http://www.play-hookey.com/digital/ Clocked SR-Latch http://www.play-hookey.com/digital/ http://www.play-hookey.com/digital/ S1 R1 http://www.play-hookey.com/digital/sequential/clocked_rs_latch.html
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– 5 – CSCE 211H Fall 2015 State Table SR clocked Flip-flop ClkSRQS1R1Q* (next) 0 1000 1001 1010 1011 1100 1101 1110 1111 S1 R1
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– 6 – CSCE 211H Fall 2015 Clocked SR-Latch Implementation 74LS00 S R CP Q Qbar
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– 7 – CSCE 211H Fall 2015 74 LS10
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– 8 – CSCE 211H Fall 2015 Building a JK from Chips Vcc CP J K GND Q QN 74LS10 74LS00
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– 9 – CSCE 211H Fall 2015 74LS49 – Seven segment display driver 74LS49/74LS47 Inputs BCD digit (DCBA) (D is the MSB) Outputs abcdefg – the seven segment driver lines Schematic fig 5-45 Note negation of inputs to or-gate x’ + y’ = (x’ + y’)’ ’ = (x’’. y’’)’ = (x. y)’ It’s a NAND! Truth table fig 5-21
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– 10 – CSCE 211H Fall 2015 Hints on Circuits Hook up MUX BCD-to-7Seg 7Segment Steps 1. Vcc,GND to all 2. put 330 ohm resistors in series with anode connections to LSD5061-11 (MAN71A) hooking them to Vcc 3. Test the 7-segment display hooking the individual cathodes to GND 4. Hook up outputs from 74LS47 to cathode inputs of 7-segment display 5. Hook the LampTest (pin 3) of the 74LS47 to GND, all segments should light up. 6. Hook up A1,A0 inputs of 74LS47 to Mux outputs, A2 and A3 should be GND 7. Test various values of select lines and mux inputs
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– 11 – CSCE 211H Fall 2015 Arduino kits
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– 12 – CSCE 211H Fall 2015 Getting Started with Arduino Introduction: What Arduino is and why you'd want to use it. Introduction Installation: Step-by-step instructions for setting up the Arduino software and connecting it to an Arduino Uno, Mega2560, Duemilanove, Mega, or Diecimila. Windows Mac OS X Linux (on the playground wiki) Linux Environment: Description of the Arduino development environment and how to change the default language. Environment Libraries: Using and installing Arduino libraries. Libraries Troubleshooting: Advice on what to do if things don't work. Troubleshooting http://arduino.cc/en/Guide/HomePage
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– 13 – CSCE 211H Fall 2015 Installing Arduino on Linux
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– 14 – CSCE 211H Fall 2015 Teams? 10 People; 5 teams
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– 15 – CSCE 211H Fall 2015 Seven segment Display
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– 16 – CSCE 211H Fall 2015 74LS47 – BCD to Seven Seg. Driver
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– 17 – CSCE 211H Fall 2015 74LS153 Dual 4 input MUX
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– 18 – CSCE 211H Fall 2015 Hooking them Up 74LS47 74LS153
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– 19 – CSCE 211H Fall 2015 Transition Table for Clocked SR flip-flop SRQ(t) Q* or Q(t+1) 000 001 010 011 100 101 110 111
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– 20 – CSCE 211H Fall 2015 J-K Flip Flop JKJK http://www.play-hookey.com/digital/jk_nand_flip-flop.html
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– 21 – CSCE 211H Fall 2015 Transition Table for JK Flip Flop JKQ(t) Q* or Q(t+1) 000 001 010 011 100 101 110 111
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– 22 – CSCE 211H Fall 2015 The D Flip Flop One input D D = 0 Q(t+1) = 0 D = 1 Q(t+1) = 1
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– 23 – CSCE 211H Fall 2015 The T Flip Flop One input T T = 0 No change Q(t+1) = Q(t) T = 1 Complement Q(t+1) = Q(t)’
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– 24 – CSCE 211H Fall 2015 Excitation Tables What inputs do we need to supply to the flip-flop do achieve the desired state transition? Q(t)Q(t+1)SR 00 01 10 11
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– 25 – CSCE 211H Fall 2015 Excitation Tables: JK What inputs do we need to supply to the flip-flop do achieve the desired state transition? Q(t)Q(t+1)JK 00 01 10 11
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– 26 – CSCE 211H Fall 2015 Excitation Tables: T What inputs do we need to supply to the flip-flop do achieve the desired state transition? Q(t)Q(t+1)JK 00 01 10 11
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– 27 – CSCE 211H Fall 2015 Characteristic Equations Next state as a function of current state and inputs Q* = F(Q, S, R) // Q* = Q(t+1) Q* = F(Q, S, R) // Q* = Q(t+1) Table 7-1 of text For MS S-R flip-flop Q*
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– 28 – CSCE 211H Fall 2015 Characteristic Tables and Equations Characteristic Tables for a flip flop Describes next state Q* [or Q(t+1)] as function of inputs and in terms of current state Q [or Q(t)] Characteristic Equation specifies the next state as a function of current state and inputs (as an equation)
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– 29 – CSCE 211H Fall 2015 Table 7-1 Characteristic Equations Device Characteristic Equation S-R Latch Q* = S + R’ Q D-latch Q* = D D flip-flop with Enable Q* = EN. D + EN’. Q Master-Slave SR flip-flop Master-Slave JK Edge Triggered JK T flip-flop T with Enable
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– 30 – CSCE 211H Fall 2015 Excitation Tables What inputs need to be given to cause a specific state transition?
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– 31 – CSCE 211H Fall 2015 Edge Triggered D Flip-Flops Positive edge triggered D Q C D Q C CLK D Suppose D=0 for sometime then Qm = 0 and Q = 0 Then tracing this through setting D=1, CLK=1 The master changes when the clock CLK goes to 0 This means QM goes to 1, and then when the CLK goes to 1 Q becomes 1 masterslave QM
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– 32 – CSCE 211H Fall 2015 State-machine structure (Mealy) typically edge-triggered D flip-flops output depends on state and input
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– 33 – CSCE 211H Fall 2015 State-machine structure (Moore) output depends on state only typically edge-triggered D flip-flops
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– 34 – CSCE 211H Fall 2015 TBird Lights State machine problem
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– 35 – CSCE 211H Fall 2015 TBird Lights
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– 36 – CSCE 211H Fall 2015
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– 37 – CSCE 211H Fall 2015 Bouncing Switches Connecting the “red” terminals below should change the output from 0 to 1. However, this change is not instantaneous; switches bounce http://www.ganssle.com/debouncing.pdf http://www.ganssle.com/debouncing.pdf
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– 38 – CSCE 211H Fall 2015 Switch Bouncing When contact is made, it is not made instantaneously and smoothly. There is contact, it bounces open, contact again, open again … finally settling down after a few milliseconds (840 μsec = 840*10 -6 sec) http://www.ganssle.com/debouncing.pdf
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– 39 – CSCE 211H Fall 2015 Debouncing with a SR latch Fig 8-6 p 669
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