1. OUT IN 1 2 3 74LS00 1 7 8 14 +5 Gnd +5 Figure 1: (a) Logic Level Measurement (Measure voltage at OUT node). (b) Power Supply Wiring.

2. In Out t PD t fall t rise Figure 2: Timing Characteristics (10%, 50%, 90% marked).

3. 1 234 5 6 13 121110 Figure 3: Ring Oscillator (using a 74LS04).

4. +5 1 2 3 4 5 6 8 9 10 11 12 13 GLITCH 1.8432 MHz Xtal 1 23 4 +5 Figure 4: Glitch Measurement Circuit (74LS00). CLK

5. 74LS393 1A1B1C1D CLK1 CLK2 2A2B 2C2D CLR1 CLR2 1.8432 MHz Xtal 1 2 3 4 1 2 12 1110 9 8 13 6543 +5 Figure 5: Clock and Ripple Counter.

6. QaQb QdQc P T LD CLR AB C D RCO 74LS163 +5 QaQb QdQc P T LD CLR AB C D RCO 74LS163 1.8432Mhz 1 2 3 456 7 9 10 11121314 15 1 2 3456 7 9 10 11121314 15 +5 Figure 6: Synchronous Counter Wiring

7. Figure 7: The first four digits on the seven-segment display

8. Figure 8: Block diagram for testing your decoding logic a b c d e f g 7-segment LCD YOUR LOGIC HERE! VDD 4.7K VDD 4.7K dipswitch