2. Content Project Goals. Workflow Background. System configuration. Working environment. System simulation. System synthesis. Benchmark. Multicore.

3. Project Goals Project Goal: building a SoC based on a multicore implementation of the OpenRISC CPU. Term A Goals: 1. Building a SoC based on an OpenRISC CPU. 2. Benchmarking the system for future reference. 3. Exploring multicore architectures.

4. Term A - Workflow Learning the OpenRISC architecture. Learning Verilog HDL. Choosing a SoC. Getting familiar with the work environment. Configuring the SoC. Simulation and Synthesis. Benchmarking for future reference. Choosing a multicore architecture.

5. The OpenRisc CPU The OpenRISC 1200 is a synthesizable CPU core maintained by developers at OpenCores. The OR1200 design is an open source (under LGPL GNU) implementation of the OpenRISC 1000 RISC architecture 1-way set associative 4KB instruction and data cache. Harvard architecture. No divide implementation (done by software). Disabled DSP unit. Includes a Timer.

6. Choosing the SoC orpSoC minSoC Reference design. Different FPGA’s needs different ports. Developed by OpenCores. More IP cores: UART. Ethernet. VGA. AC97… Suitable for running Linux. Generic design. Developed by Raul Fajardo. Minimal implementation, only: UART Ethernet. Only the basics, meant to be configured. simpler, but more advanced RAM model. Less FPGA resources.

7. Configuring minSoC On-Chip memory blocks

8. FPGA used XUPV5 Board

9. Work Environment Windows PlanAhead (synthesis). iMPACT (transferring design to FPGA). Terminal for UART connection. Ubuntu Icarus & or1ksim (simulation). GTKwave (viewing waves created by Icarus). GNU OpenRisc toolchain (or32-elf): binutils, GCC and GDB (compilation and debugging). newlib and uclibc (minimal C libraries). And others …

11. Simulation – workflow The code is compiled with or32-elf-gcc. The binary file is converted to a hex file. The hex file is written into the memory HDL file. The system is simulated using Icarus. UART output is redirected to the terminal. Wave file can be viewed using GTKwave.

12. Simulation – the code

13. Simulation - results 32 36 2f 32 2f 32 30 31 34 20 2d 20 48 65 6c 6c 6f 20 57 6f 72 6c 64 2e 26/2/2014 - Hello World.

14. Synthesis – workflow The hex file is written to the memory model. RTL design is transferred to planAhead. Synthesis. Generating Bitstream file. Using iMPACT to program the FPGA. UART output is displayed on the terminal.

15. Synthesis

16. Benchmarking We used Dhrystone benchmark. Dhrystone is a synthetic computing benchmark program developed in 1984. intended to represent the system’s integer performance – doesn’t contain floating point operations. Dhrystone tries to represent the result more meaningfully than MIPS using DMIPS, a count of the number of program iteration completions per second. We measured a 16257.6 Dhrystone score (0.37 DMIPS/MHz).

17. MultiCore System bus isn’t aware of multicores All cores have the same address. Cache coherency. System bus is aware of multicores. Each core has different address Cache coherency.

18. MultiCore – Tiled architecture Scalable. CPU remains intact. NoC handles cache coherencies. NoC handles resources allocation.

19. Hurdles along the way Outdated hardware (RS232). Lack of proper documentation. Working on several IP cores, written by different people. Writing code for embedded system, not for an OS. RTL code is targeting different FPGAs. On a bug, is it hardware or software related.

20. Achievements Learned Verilog HDL. Learned Linux OS basics. Learned to work with Xilinx FPGAs and software. Design on multiple levels, from a hardware RTL design to a C software. Learned New hardware architecture and software toolchain. Project goals: 1. Building a SoC based on an OpenRISC CPU………. 2. Benchmarking the system for future reference….. 3. Exploring multicore architectures………………………

21. Thank you.