Presentation is loading. Please wait.

Presentation is loading. Please wait.

Scalar Data Types and Operations 大同大學 資訊工程系 副教授 鄭福炯

Published byThomas Greer Modified over 8 years ago

Similar presentations

Presentation on theme: "Scalar Data Types and Operations 大同大學 資訊工程系 副教授 鄭福炯"— Presentation transcript:

1 Scalar Data Types and Operations 大同大學 資訊工程系 副教授 鄭福炯 (cheng@cse.ttu.edu.tw)

2 © Fu-Chiung Cheng VHDL Ch02 2 Type Type of a data object defines – the set of values that the object can assume and – the set of operations that can be performed on those values Type: scalar types, access types, file types and composite types

3 © Fu-Chiung Cheng VHDL Ch02 3 Lexical Elements of VHDL Lexical elements of VHDL: comments, identifiers, reserved words, special symbols, numbers, characters, strings, bit strings Comments: – A comment line in VHDL is represented by two successive dashes “--”. – A comment extends from “--” to the end of the line. – See page 192 examples

4 © Fu-Chiung Cheng VHDL Ch02 4 Lexical Elements of VHDL Identifiers: – Identifiers are used to name items – Use meaningful name – Identifiers can be arbitrarily long – Some Rules: must start with an alphabetic letter. can contain alphabetic letters, decimal digits and underline character “_”. can not end with “_”. can not contain successive “_”.

5 © Fu-Chiung Cheng VHDL Ch02 5 Lexical Elements of VHDL Legal and illegal examples: – See page 18 Extended identifiers – Can contain any sequence of characters – Is written by enclosing the characters between ‘\’ characters – Examples: \data bus\, \global.clock\, \923\

6 © Fu-Chiung Cheng VHDL Ch02 6 Lexical Elements of VHDL Reserved Words – Reserved words are used to denote special constructs that form a model – Can not be used as identifiers – Is listed in Figure 1-15 on page 19

7 © Fu-Chiung Cheng VHDL Ch02 7 Lexical Elements of VHDL Special Symbols: – Operators: +, -, &, *, /,.,, |, /=, :=, >=, – To delimit parts of language constructs and as punctuation: “, ‘, (, ), “,”, :, ;, – array indices: [] Numbers: – Integer literals: 23, 0, 146, 56E5, 1E+12, 2#11111101#, 16#12FD”, 2#1111_1101# – Real literals: 23.1, 0.0, 3.14159, 1.234E09

8 © Fu-Chiung Cheng VHDL Ch02 8 Lexical Elements of VHDL Characters – ‘A’~’Z’, ‘a’-’z’, ‘,’, Strings – A sequence of characters – “data bus”, “923” (use & operator) – Binary digits: B for binary, O for octal, X for hexadecimal (B”01010111”, X”97”)

9 © Fu-Chiung Cheng VHDL Ch02 9 Syntax Descriptions Extended Backus-Naur Form to describe the rules of VHDL syntax EBNF divides a language into syntactic categories: Variable assignment: – Variable_Assignment  target := Expression; – x := y + 1; Function_Call  name [( Association_Lis t) ] – zero or one

10 © Fu-Chiung Cheng VHDL Ch02 10 Syntax Descriptions Optional operator “{}” – process is { process_declarative_item } begin { sequential_statement } end process; – zero or more Iterative operator “{…}” – identifier_list <= identifier, {…} | identifier – one or more

11 © Fu-Chiung Cheng VHDL Ch02 11 Syntax Descriptions Choice operator “|” – mode <= in | out | inout – one of the many Parenthetic grouping ( ) – Term  Factor { (*|/|mod|rem) Factor)}

12 © Fu-Chiung Cheng VHDL Ch02 12 Constant Declaration EBNF: constant_decl  constant id {,… }: subtype_indication [:= expr ]; Examples: – constant NUMBER_OF_BYTE: integer := 4; – constant SIZE, COUNT: integer := 255;

13 © Fu-Chiung Cheng VHDL Ch02 13 Variable Declaration and Assignment Variables act as placeholders for quantities that change during simulation. EBNF: variable_decl  variable id {,… }: subtype_indication [:= expr ]; Examples: – variable index, sum : integer := 0; – variable_assign <= [labe l: ] i d:= exp r; Can be used in process block only – pc := 1; – index := index + 1;

14 © Fu-Chiung Cheng VHDL Ch02 14 Type Every name or id in VHDL has an associated “type”. The “type” determines the operations that can be applied to the name. VHDL along with its packages provides pre- defined types. Additionally the user can define new types.

15 © Fu-Chiung Cheng VHDL Ch02 15 Type Declarations EBNF” type_decl <= type id is type_definition ; Useful when pre-defined types are insufficient. Examples: – type apples is range 0 to 100; – type oranges is range 0 to 100; – apples may not be assigned to variable oranges Default value is left hand side of range.

16 © Fu-Chiung Cheng VHDL Ch02 16 Type Declarations User defined type – If we define our own types for ports, the type names must be declared in a package (similar to a header file). – Example: package int_types is type Small_Int is range 0 to 255; end package int_type

17 © Fu-Chiung Cheng VHDL Ch02 17 Type Declarations User defined type – Example use work.int_type.all; entity SmallAdder is Port (a,b: in small_int; s: out small_in) end enitity small_adder

18 © Fu-Chiung Cheng VHDL Ch02 18 Integer type “integer” is a pre-defined type used to represent whole numbers. – variable x, y : integer ; VHDL standard requires that the implementation be able to represent numbers from –2^31 + 1 to 2^31 – 1. User can define new “integer” types.

19 © Fu-Chiung Cheng VHDL Ch02 19 Integer type EBNF: – type_decl <= type identifie r is int_type_def n; – int_type_defn <= range expr (to | downto ) expr Examples: – type month is range 1 to 12 ; – type count_down is range 10 downto 0;

20 © Fu-Chiung Cheng VHDL Ch02 20 Integer type : operations Addition: +, Subtraction or negation: -, Multiplication: *, Division: / Modulo: mod – a = b*n + (a mod b), sign of b, n: integer – (-5) mod 3 = 1 Remainder: rem – a = (a/b)*b + (a rem b), sign of a – (-5) rem 3 = 1 Absolute value: abs Exponentiation: ** Logical: =, /=,, =

21 © Fu-Chiung Cheng VHDL Ch02 21 Floating-point type “real” is a pre-defined type used to represent floating-point numbers – variable x, y : real ; Similar to integers the user can also define new real types with limited range. Examples – type temp is range –273.0 to 1000.0 ;

22 © Fu-Chiung Cheng VHDL Ch02 22 Floating point type: operations Addition: + Subtraction or negation: - Multiplication: * Division: / Absolute value: abs Exponentiation: ** Logical: =, /=,, =

23 © Fu-Chiung Cheng VHDL Ch02 23 Time type Predefined physical type. type time is range implementation defined units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; end units;

24 © Fu-Chiung Cheng VHDL Ch02 24 Enumerated types Useful for giving names to a values of an object (variable or signal). Example: – type alu_func is (disable, pass, add, sub, mult, div); Predefined enum types – type character is ( ‘a’, ‘b’, ‘c’, ……….); Operations: =, /=,, = – type boolean is ( false,true); Operations: and, or, nand, nor, xor, xnor, not, =, /=,, =

25 © Fu-Chiung Cheng VHDL Ch02 25 Characters ISO 8859-Latin-1 8-bit character set – type character is ( null, soh, …. ………. ); – Example: variable command_char, terminator: character; command := ‘P’; terminator := cr;

26 © Fu-Chiung Cheng VHDL Ch02 26 Boolean Boolean is one of the most important predefined types in VHDL – type boolean is (false, true); – Operations and, or, nand, nor, xor, xnor, not – and, or, nand, nor are called “short-circuit” operators

27 © Fu-Chiung Cheng VHDL Ch02 27 Bit type Bit is also a predefined enumerated type – type bit is (‘0’, ‘1’); – Operations Logical: =, /=,, = Boolean: and, or, nand, nor, xor, xnor, not Shift:sll, srl, sla, sra, rol, ror

28 © Fu-Chiung Cheng VHDL Ch02 28 Standard logic Since VHDL is designed to modeling digital hardware, it is necessary to include types to represent digitally encoded values type std_logic is (’U’, -- Uninitialized ‘X’, -- Forcing Unknown ‘0’, -- Forcing zero ‘1’, -- Forcing one ‘Z’, -- High impedance ‘W’, -- Weak Unknown ‘L’, -- Weak zero ‘H’, -- Weak one ‘_’); -- don’t care

29 © Fu-Chiung Cheng VHDL Ch02 29 Subtypes Sub types are useful for limiting the range of base type Examples: type month is 1 to 31; subtype working_day is month range 1 to 3; variable x,y : month; variable z : working_day; y = x + z; subtype natural is integer range 0 to biggest_integer; subtype positive is integer range 1 to biggest_integer;

30 © Fu-Chiung Cheng VHDL Ch02 30 Type Conversion Integer to real: read(123) Real to integer: integer(3.6) See Chap 4 for more detail.

31 © Fu-Chiung Cheng VHDL Ch02 31 Attributes of Scalar Types T’left : first (leftmost) value of T T’right : last (rightmost) value of T T’low : least value of T T’high : highest value of T T’ascending : true if T is ascending, false otherwise T’image(x) : A string representing the value of x T’value(s) : The value in T that is represented by s.

32 © Fu-Chiung Cheng VHDL Ch02 32 Example type set_index is range 21 downto 11; set_index’left = 21 set_index’right = 11 set_index’low = 11 set_index’high = 21 set_index’ascending = false set_index’image(14) = “14” set_index’value(“20”) = 20 Restrictions on coding style for RTL model

33 © Fu-Chiung Cheng VHDL Ch02 33 Attributes of Scalar Types Discrete types are integer and all enumerated types. – T’pos(x): position of x in T – T’val(n): value in T at position n – T’succ(x): successor of x in T – T’pred(x): predecessor of x in T – T’leftof(x): value in T at position one left of x – T’rightof(x): value in T at position one right of x

34 © Fu-Chiung Cheng VHDL Ch02 34 Example type logic_level is (unknown, low, undriven, high); logic_level’pos(unknown) = 0 logic_level’val(3) = high logic_level’succ(unknown) = low logic_level’pred(undriven) = low

35 © Fu-Chiung Cheng VHDL Ch02 35 Expression and Operators Primary values that can be used in expressions: – Literal values – Identifiers representing data objects (constants, variables) – Attributes that yield values – Qualified expressions – Type-converted expressions and – Expressions in parentheses

36 © Fu-Chiung Cheng VHDL Ch02 36 Expression and Operators VHDL operators – See page 53~54

Download ppt "Scalar Data Types and Operations 大同大學 資訊工程系 副教授 鄭福炯"

Similar presentations

INTRO TO VHDL Appendix A: page 779 - page 831 1. VHDL is an IEEE and ANSI standard. VHDL stands for Very High Speed IC hardware description language.

INTRO TO VHDL Appendix A: page page VHDL is an IEEE and ANSI standard. VHDL stands for Very High Speed IC hardware description language.
Chapter 11 Verilog HDL Application-Specific Integrated Circuits Michael John Sebastian Smith Addison Wesley, 1997.

Chapter 11 Verilog HDL Application-Specific Integrated Circuits Michael John Sebastian Smith Addison Wesley, 1997.
1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.

1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.
Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of.

Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of.
ECE C03 Lecture 161 Lecture 16 Introduction to VHDL Prith Banerjee ECE C03 Advanced Digital Design Spring 1998.

ECE C03 Lecture 161 Lecture 16 Introduction to VHDL Prith Banerjee ECE C03 Advanced Digital Design Spring 1998.
Comprehensive VHDL Module 6 Types November 2000. 6-2 Comprehensive VHDL: Types Copyright © 2000 Doulos Types Aim ©To understand the use and synthesis.

Comprehensive VHDL Module 6 Types November Comprehensive VHDL: Types Copyright © 2000 Doulos Types Aim ©To understand the use and synthesis.
VHDL Data Types Module F3.1. VHDL Data Types Scalar Integer Enumerated Real (floating point)* Physical* Composite Array Record Access (pointers)* * Not.

VHDL Data Types Module F3.1. VHDL Data Types Scalar Integer Enumerated Real (floating point)* Physical* Composite Array Record Access (pointers)* * Not.
Data Types. Composite Date Types n Arrays –Single and multi-dimensional –Arrays are single Type n Records –Records are mixed types.

Data Types. Composite Date Types n Arrays –Single and multi-dimensional –Arrays are single Type n Records –Records are mixed types.
ECE C03 Lecture 121 Lecture 12 Introduction to VHDL Hai Zhou ECE 303 Advanced Digital Design Spring 2002.

ECE C03 Lecture 121 Lecture 12 Introduction to VHDL Hai Zhou ECE 303 Advanced Digital Design Spring 2002.
ELEN 468 Lecture 191 ELEN 468 Advanced Logic Design Lecture 19 VHDL.

ELEN 468 Lecture 191 ELEN 468 Advanced Logic Design Lecture 19 VHDL.
0 Chap. 2. Types, Operators, and Expressions 2.1Variable Names 2.2Data Types and Sizes 2.3Constants 2.4Declarations Imperative Programming, B. Hirsbrunner,

0 Chap. 2. Types, Operators, and Expressions 2.1Variable Names 2.2Data Types and Sizes 2.3Constants 2.4Declarations Imperative Programming, B. Hirsbrunner,
The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL Adrian Ilie COMP 14 Introduction to Programming Adrian Ilie June 27, 2005.

The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL Adrian Ilie COMP 14 Introduction to Programming Adrian Ilie June 27, 2005.
第6章 VHDL NUMBERS, STRINGS, AND EXPRESSIONS 義守大學電機工程學系 陳慶瀚

第6章 VHDL NUMBERS, STRINGS, AND EXPRESSIONS 義守大學電機工程學系 陳慶瀚
Chapter 2: Introduction to C++.

Chapter 2: Introduction to C++.
JavaScript, Third Edition

JavaScript, Third Edition
VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language  VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language  VHSIC: Very High Speed Integrated Circuit 7/2/ R.H.Khade.
Concordia University 1 Lecture #8 In this lecture we will cover the following material: The standard package, The std_logic_1164  Objects & data Types.

Concordia University 1 Lecture #8 In this lecture we will cover the following material: The standard package, The std_logic_1164  Objects & data Types.
Reconfigurable Computing - VHDL - Types John Morris Chung-Ang University The University of Auckland.

Reconfigurable Computing - VHDL - Types John Morris Chung-Ang University The University of Auckland.
1 Part I: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

1 Part I: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.
VHDL – Dataflow and Structural Modeling and Testbenches ENGIN 341 – Advanced Digital Design University of Massachusetts Boston Department of Engineering.

VHDL – Dataflow and Structural Modeling and Testbenches ENGIN 341 – Advanced Digital Design University of Massachusetts Boston Department of Engineering.

Similar presentations

Ads by Google