1. COMP 1321 Digital Infrastructure Richard Henson University of Worcester October 2015

2. Week 3: The Fetch-Execute Cycle n n Explain the instruction set of a typical CPU n n Understand the sequential way a CPU works, using its instruction set n n Understand how registers and memory addresses are used to process a CPU instruction and store the results

3. CPUs and the SAM n CPUs very, very, very fast n SAM is a CPU simulator  processes one CPU cycle at a time  designed to allow you to watch what happens during processing  instructions can require several cycles

4. What is “Processing”? n Mostly, calculations by ALU:  need data input »from register »from external memory  need to store output »from register »from external memory n Could also be just a command, no data

5. CPU types n Most frequently used:  Intel 8086 family  Motorola (esp. 68000 family)  ARM (many mobile phones) n We’ll focus on Intel 8086 family  dates back to original IBM PC…

6. Role of “Registers” n Memory stores inside the CPU  just the right size “word” of data for ALU »typically 1, 2, 4 bytes i.e. very small! n Advantage: CPU reads/writes data very very quickly to/from the registers

7. Architecture and Buses n Design of CPU  internal connections  external connections to motherboard »data bus (same word as registers) »address bus (depends on no of memory locations) »control bus (messages to/from components)  layout of components on motherboard

8. 0 1 4 6 8 6 8 4 Registers: high-speed memory on the CPU chip Parking places for data on the move AX and BX registers are used for ALU operations MAR is memory address register, 4 in eg. Result, 6+8=14, will go into memory cell address 4 AX BX MAR R Registers (from last week…)

9. Adding Numbers Instruction Memory 0 1 2 mar 3 4 add ax, bx 8 5 7 6 1 BX AX Add ax,bx 7 For example … … this means ‘ add ax to bx, put the answer in ax’ 8 8 7 15

10. ip Data Memory Instruction Memory 0 1 4 mar The computer so far… (identify & name components)

11. Instruction Memory A couple of extra registers.. Data Memory 0 1 4 Instruction Register Memory Data Register 2 8 34 2 Data Address add ax,bx 1.Line of code goes in… 2.Electrical bit signals come out 2. 1. Energize ax Energize bx Select ALU “add"

12. Moving data into Registers (ie from specified location) Instruction Memory 0 1 2 mar 3 4 mov ax, [1] 8 5 8 7 6 1 BX AX mov ax, [1] mov bx, [2] 7 for example …

13. Moving data into Memory Instruction Memory 0 1 2 mar 3 4 mov [3], ax 8 5 8 7 6 1 BX AX mov [3], ax mov [0], bx 7 For example … 8 7

14. 8086 CPU family registers n 8086 chip always used a 16-bit word  SAM simulates an 8-bit word »popular on most early microcomputers… n Typical 8086 registers:  general purpose data: AX, BX, CX, DX  specific use e.g. »program counter (PC): instruction address in memory »stack pointer SP): address of the top of the “stack”

15. Data and Addressing n General purpose register contents…  data  memory address that points to data n Convention:  data written as hexadecimal equivalent »e.g. 4A  memory location also has square brackets »e.g. [4A]

16. CPU Instructions n Used to tell the CPU what to do… n MOV is for moving data around…  MOV AX, 4A – move “4A” into AX register  MOV AX, [4A] – move data contained in address 4A into AX register n Many other instructions; range of operations…  collectively known as an instruction set  each CPU family has its own unique codes

17. 8086 in practice n Four 16-bit General Purpose registers  each gen register (e.g. AX) can be read/written to upper (AH) & lower (AL) byte AH AL BL BH CH DH CL DL AX BX CX DX upper byte lower byte

18. Another 8086 Instruction: ADD n Takes values from two registers n Adds them together n Deposits results back in one of the registers n Which one?  the register that appeared first  e.g. “MOV, AX, BX” puts result in AX

19. Fetch-Execute Cycle 1. Fetch instruction from memory 2. Decode the instruction and read any registers 3. Do any ALU operations (execute units) 5. Write back results to registers (Organization and Control) add ax, bx 4. Do any Memory Access ALU <- ax ALU <- bx ax + bx (Data cache) ax <- ALU None needed

20. add ax, bx add ax 0 1 4 3 2 bx Fetch-Exec : State 1 Instruction Fetch 8 3 7 1 9 3 1 AX BX

21. 0 1 4 3 2 Fetch-Exec : State 2 Decode, Register Operations 8 3 7 1 9 add ax, bx add axbx 3 1 3 1 AX BX

22. 0 1 4 3 2 Fetch-Exec : State 3 ALU Operation 8 3 7 1 9 add ax, bx add axbx AX BX 3 1 4

23. 0 1 4 3 2 Fetch-Exec : State 4 Memory Access 8 3 7 1 9 add ax, bx add axbx AX BX 3 1 4

24. 0 1 4 3 2 Fetch-Exec : State 5 Register Write 8 3 7 1 9 add ax, bx add axbx BX 3 1 4 4

25. Fetch-Execute Cycle 1. Fetch instruction from memory 2. Decode the instruction and read any registers 3. Do any ALU operations (execute units) 5. Write back results to registers (Organization and Control) mov ax, [1] 4. Do any Memory Access Read the ‘1’ Put ‘1’ into MAR Data into ax Read memory at addr ‘1’

26. mov ax, [1] mov ax 0 1 4 3 2 1 Fetch-Exec : State 1 Instruction Fetch 8 3 7 1 9

27. mov ax, [1] mov ax 0 1 4 3 2 1 Fetch-Exec : State 2 Decode, Register Operations 8 3 7 1 9

28. mov ax, [1] mov ax 0 1 4 3 2 1 Fetch-Exec : State 3 ALU Operation 1 8 3 7 1 9

29. mov ax, [1] mov ax 0 1 4 3 2 1 Fetch-Exec : State 4 Memory Access 1 8 3 7 1 9 8

30. mov ax, [1] mov ax 0 1 4 3 2 1 Fetch-Exec : State 5 Register Write 1 8 3 7 1 9 8 8

31. 8088: Brains of the IBM PC

32. Inside the 8088 address bus address adder gen registers External buses ALU

33. 5 1 2 3 4 1.Fetch 2.Decode 3.ALU 4.Mem Ops 5.Reg Write Pentium (same family)

34. Programming a CPU n CPU programming code written as assembly language  each family has its own instruction set n Programming syntax depends on the  CPU/instructions  how they should be used  Intel 8086 assembly language used for CPUs that support PC platforms

35. Example 8086 Assembly Language   MOV AH,08   INT 21   MOV DL,AL   MOV AH,02   INT 21   MOV AH,4C   INT 21

36. So THAT’S how it all works! now you try it on SAM2… Next week: a focus on writing programs and i/o