1. A Continuously Adapting Floating-Gate Node Jeff Dugger and Paul Hasler School of ECE Georgia Institute of Technology http://users.ece.gatech.edu/~jeffd

2. What is an Adaptive Node? w1w1 w2w2 w N-1 wNwN x1x1 x2x2 x N-1 xNxN y...... + Unsupervised Learning: Supervised Learning: Computation Adaptation x y

3. Computing in Memory Single-synapse computation, storage, and adaptation in about the space of a 4-bit EEPROM cell. 0.25, 1 cm chip 16 Meg EEPROM cells4 million synapses Density is very important --- computing in the memory

4. Single Transistor Floating-Gate Synapse: Computation Input VoltageOutput Current Traditional Transconductance Amplifier bias transconductance biassignal

5. Single Transistor Floating-Gate Synapse: Storage Capacitive Voltage Divider Floating node acts as non-volatile voltage memory

6. Single Transistor Floating-Gate Synapse: Storage + Computation + Transconductance AmplifierCapacitive Divider Adaptive weight Capacitor-coupled transconductance

7. Single Transistor Floating-Gate Synapse: Adaptation pFET Floating-Gate Synapse From KCL at floating-gate: Adapts floating-gate charge using: Tunneling Injection

8. Correlation Learning Rule ()

9. Adaptive Floating-Gate Node

10. Phase Correlations cos(  t)sin(  t) sin(  t +  ) 050100150200250300350 degrees Synapse 2 Current (  A) Synapse 1 Current (  A) 0 0 -0.5 0.5

11. Synapse Weight Convergence Desired signal sin(  t)sin(3  t) Time(s) Synaps e Curr ents ( 100nA) 3.4s I 2 I 1 sin(  t)sin(3  t)sin(  t) sin(0.7  t)  = 6.5s I 1 bias = 5.4mA, 2 bias = 3.7mAI

12. Learning a Square Wave 102030405060708090 -2 0 1 2 3 Output Current (  A) Time (ms) 0 square(  t) sin(  t)sin(3  t)

13. Adaptive Floating-Gate Networks Multiple Nodes Single Layer Multiple Layers Networks From Node to System From Device to Node pFET Floating-Gate Synapse One device computation, weight storage, and adaptation Correlation learning rule Multiple Synapses Single Node

14. Analog Computing Arrays