1. DIGITAL SYSTEMS Programmable devices PLA-PAL Rudolf Tracht and A.J. Han Vinck

2. content Programmable Logic –Programmable Logic Array PLA –Programmable Array Logic PAL

3. Programmable Logic Array A PLA can implement m functions of n variables, where each function (in SoP form) can have up to k product terms PLA is programmed to select the literals in each product term and select the product terms in each function General structure: –For a ROM, the number of product terms is k = 2 n –For a PLA, k < 2 n NAND n-inputm-output k product lines

4. inputs NAND array outputs NAND array product terms Cont’d Pre-fabricated building blocks of many NAND gates "personalized" by making or breaking connections among the gates n k m programmable array block diagram for sum of products form

5. Before programming All possible connections are available before "programming" Note: conversion to NAND a  b + c  d = ((a  b)‘  (c  d)‘)‘ F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A

6. after programming Note: conversion to NAND a  b + c  d = ((a  b)‘  (c  d)‘)‘ Unwanted connections are "blown„ A C B F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A

7. example: F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A personality matrix 1 = uncomplemented in term 0 = complemented in term – = does not participate 1 = term connected to output 0 = no connection to output input side: output side: productinputsoutputs termABCF0F1F2F3 AB11–0110 B'C–010001 AC'1–00100 B'C'–001010 A1––1001 reuse of terms Shared product terms among outputs

8. PLA Two-level AND-OR device –can be programmed to realize any sum-of-products Limitations: –Number of inputs, outputs, product terms Field programmable: –attractive in a research environment –Programm can be simulated and changed immediately

9. ANDing and ORing

10. Example of basic functions Multiple functions of A, B –F1 = A B –F2 = A + B –F3 = A' B' –F4 = A' + B' –F5 = A xor B AB F1F2F3F4F5 00 00110 01 01011 10 01011 11 11000 A B Homework: do the same for 3 variables

11. Programmable Aray Logic PAL limited connections are available before "programming" –constrained topology –faster and smaller OR plane

12. 0 1 X 1 0 1 X 1 0 1 X X 0 1 X X D A B C minimized functions: W = A X = B + A Y = BC‘ + B‘C Z = C'D + C D' ABCDWXYZ00000000000100010010001100110010010001100101011101100101011101001000110010011101101–––––11––––––ABCDWXYZ00000000000100010010001100110010010001100101011101100101011101001000110010011101101–––––11–––––– 0 0 x 1 0 0 x 1 0 0 x x 0 0 x x D A B C K-map for WK-map for X 0 1 X 0 0 1 X 0 1 0 X X 1 0 X X D A B C K-map for Y example BCD to Gray code converter K-map for Z 0 0 X 0 1 1 X 1 0 0 X X 1 1 X X D A B C

13. decoder 0n-1 Address 2 -1 n 0 1111 word[i] = 0011 word[j] = 1010 bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches) j i internal organization word lines (only one is active – decoder is just right for this) recall Two dimensional array of 1s and 0s –entry (row) is called a "word" –width of row = word-size –index is called an "address" –address is input –selected word is output

14. ROM vs. PLA ROM approach advantageous when –design time is short (no need to minimize output functions) –most input combinations are needed (e.g., code converters) –little sharing of product terms among output functions ROM problems –size doubles for each additional input –can't exploit don't cares PLA approach advantageous when –design tools are available for multi-output minimization –there are relatively few unique minterm combinations –many minterms are shared among the output functions PAL problems –constrained fan-ins on OR plane

15. structures for two-level logic ROM – full AND plane, general OR plane –cheap (high-volume component) –can implement any function of n inputs –medium speed PAL – programmable AND plane, fixed OR plane –intermediate cost –can implement functions limited by number of terms –high speed (only one programmable plane that is much smaller than ROM's decoder PLA – programmable AND and OR planes –most expensive (most complex in design, need more sophisticated tools) –can implement any function up to a product term limit –slow (two programmable planes)