1. MICAS Department of Electrical Engineering (ESAT) Design of EMI-Suppressing Power Supply Regulator for Automotive electronics October 11th, 2006 Junfeng Zhou Promotor: Prof. Wim Dehaene KULeuven ESAT-MICAS

2. MICAS Department of Electrical Engineering (ESAT) Part I: Introduction Part II: Low Noise Power Supply–EMI-Suppressing Regulator Principles Design Simulation Calculation Chip Details Measured Results Part III: Possible Improvements Part IV: Future work Outline

3. MICAS Department of Electrical Engineering (ESAT) Part I: Introduction (EMI)radiated emission Electro-Magnetic Interference (EMI) and radiated emission have become a major problem for automotive electronics, di/dt Radiated emission is mostly a consequence of di/dt on the supply lines. di/dt Although the detailed calculation of EMI noise is rather difficult, we can use the di/dt as the index, since the current loop contributes the EMI.

4. MICAS Department of Electrical Engineering (ESAT) Part II: EMI-Suppressing Regulator Previous research on Low Noise Logic Families shows that 2 major problems still remain: Static power consumption New logic family standard cell library must be designed and characterised. (large NRE cost, risk) ? Any global approach ?

5. MICAS Department of Electrical Engineering (ESAT) Diagram of EMI-Suppressing Regulator 1. Current source ensures the major di/dt reduction 2. Slow varying is key to EMC success is key to EMC success Minimize the static current 3. Minimize the static current Principles

6. MICAS Department of Electrical Engineering (ESAT) EMI-Suppressing Regulator – basic structure Determine the switching speed, Hence determine the di/dt Energy reservoir

7. MICAS Department of Electrical Engineering (ESAT) Why new structure ? 1.Simple 2.Driving capability 3.Miller effect on compensation capacitor compensation capacitor 4.Cascode device

8. MICAS Department of Electrical Engineering (ESAT) Functionality Simulation & Comparison with standard CMOS di/dt and FFT comparison with standard CMOS w/o EMI-SR and SR I Vbat I Vbat : di/dt p-p = 1.0x10 7 A/s w/o EMI-SR and SR, di/dt p-p =1.51x10 11 A/s 44dB PSD comparison di/dt comparison

9. MICAS Department of Electrical Engineering (ESAT) Maple calculation An input current step of 1 mA and 100-ps rise time was used for the calculation and simulation di/dt I stimulus

10. MICAS Department of Electrical Engineering (ESAT) Stability analysis Approximation: p1 p2 p3 z1 >3 for > 72° phase margin Stability ~ C aux /C tank p4 i in

11. MICAS Department of Electrical Engineering (ESAT) Stability analysis – Simulation vs. Calculation Spectre simulation Maple calculation Raux=1.852K, Caux=20p,Ctank=100p Stability vs. Iload φ> 72 ° Iload =192.7u A Stability vs. Iload (26.7u A ~ 72m A) φ ≥ 60 ° Worst case

12. MICAS Department of Electrical Engineering (ESAT) Current TF analysis H(s)=I VDD (s)/I in (s) (i.e. di/dt attenuation) dominant pole second pole third pole High frequency zero left half-plane zero

13. MICAS Department of Electrical Engineering (ESAT) Current TF- simulation vs. calculation Spectre simulation Maple calculation Iload =80u A, Raux=1.852K, Ctank=100p dB - 44 dB - 43 dB

14. MICAS Department of Electrical Engineering (ESAT) Maximum Attenuation Maple calculation Iload =800u A, Raux=1.852K, Ctank=100p TF vs. Caux Cut-off freq. ~ 1/Caux Large attenuation requires Large Ctank and/or small Cdb1 Cascode structure ! dB - 40 dB

15. MICAS Department of Electrical Engineering (ESAT) Caux/Ctank and ∆V DDinput ∆VDDinput Caux = 4, 8,..20 pF ∆V DDinput ~ C aux /C tank

16. MICAS Department of Electrical Engineering (ESAT) Design Strategy EMI-Suppressing Regulator design principles EMI-Suppressing Regulator design principles  Stability ~ C aux /C tank  Time domain ∆V DDinput ~ C aux /C tank More stable also means a larger ∆V DDinput More stable also means a larger ∆V DDinput  Current TF Cut-off freq: Gm/C aux Cut-off freq: Gm/C aux Max. attenuation: C db /(C db +C tank ) Max. attenuation: C db /(C db +C tank )  Design for small C db Similar story possible for Gm, g m Similar story possible for Gm, g m Caution should be exercised to maintain the stability of the EMI-suppressing regulator while designing for higher di/dt reduction EMI-suppressing regulator while designing for higher di/dt reduction

17. MICAS Department of Electrical Engineering (ESAT) EMC test chip with EMI-Suppressing Regulator SR1, MS-FF, No capa SR2, MS-FF, 1/2 PNMOS capa SR3, MS-FF, PNMOS capa SR4, MS-FF, PNMOS capa, PWR SR5, MS-FF, PNMOS capa, MIMC capa SR6, D-FF, No capa SR7, D-FF, 1/2 PNMOS capa SR8, D-FF, PNMOS capa SR9, D-FF, PNMOS capa, PWR SR10, D-FF, PNMOS capa, MIMC capa On-chip LDO PD On-chip Serial regulator PD SR1 RST Din CLK OUT SR2 RST Din CLK OUT SR9 RST Din CLK OUT SR10 RST Din CLK OUT GND LDO PD EMI regulator Ctank VDD_input Emergency block Power down block V3v3 Vbat

18. MICAS Department of Electrical Engineering (ESAT) Current source simulation results I Vbat V3v3 VDD_input Vctrl Power down enable

19. MICAS Department of Electrical Engineering (ESAT) Frequency simulation results current of Vbat di/dt p-p =8.5x10 4 [A/s] 9x10 6 load current of digital core FFT di/dt p-p =1.8x10 9 [A/s] 7x10 3 di/dt of Vbat di/dt of V3v3 40dB (EMI regulator) + 20dB (Serial regulator)

20. MICAS Department of Electrical Engineering (ESAT) Chip Details EMI Suppressing regulator Area: 1mm x 1.1mm C tank =100p F C aux = 20 p F Power transistors: Wp=5000 μm Lp= 1 μm (fixed) Technology : AMIS 0.35μm I3T80 Supply voltage : 12 V Output voltage : typ. 8V, min.5.5V Quiescent current : 30 μA

21. MICAS Department of Electrical Engineering (ESAT) Measurement Setup

22. MICAS Department of Electrical Engineering (ESAT) Measured Results (1)

23. MICAS Department of Electrical Engineering (ESAT) Measured Results (2) Load transient response I load (0 mA ~ 20 mA ) V out 10 ns 8 V 5.78 V

24. MICAS Department of Electrical Engineering (ESAT) Measured Results (3) Peak : ~ 5x T rise : ~ 7x di/dt peak : ~ 24x

25. MICAS Department of Electrical Engineering (ESAT) Measured Results (4) Peak : ~ 9x T rise : ~ 12x di/dt peak : ~ 18x

26. MICAS Department of Electrical Engineering (ESAT) Measured Results (5) di/dt TF I AC injected -3dB: 1.6 MHz -33 dB di/dt TF I AC injected -3dB: 1.8 MHz -35 dB

27. MICAS Department of Electrical Engineering (ESAT) Conclusions A Low Noise Power Supply Techniques is presented:  Control the way the current delivered to the internal digital core, hence keep the EMI under control,  Comparable reduction on di/dt noise with low noise digital cells only,  More power efficient than the low noise digital cells,  Have similar power consumption to the conventional CMOS logic,  A global approach-Can be adjusted to a wide range of chip size and power consumption level,  Measurement results match the simulation well.

28. MICAS Department of Electrical Engineering (ESAT) Part III: Possible Improvements Frequency H(s)-dB peaking

29. MICAS Department of Electrical Engineering (ESAT)  z1 – G m /C aux  z2 – parasitic zero, high frequency  p1 – Pole at V ctrl : G m /C aux  p2 – Pole at V VDD_input : g m /C tank  p3 – pole caused by compensation path, high frequency Current TF: small signal model

30. MICAS Department of Electrical Engineering (ESAT)  z1 cancel off the  p1 Make the  p2 cut-off frequency This zero is intrinsic for this feedback topology sacrifices dynamic noise performance Make  p2 dominant Make  p2 dominant Advanced compensation techniques needed Advanced compensation techniques needed Current TF: pole-zero tracking Frequency H(s)-dB  z1  p1  p2 peaking Options

31. MICAS Department of Electrical Engineering (ESAT) Key Idea : Achieving Stability Without Sacrificing Dynamic Supply Current Rejection R-C compensation Reduced Gm of OTA R eq added for moving the output pole high frequency, also for improvement of the dynamic di/dt rejection Possible solution

32. MICAS Department of Electrical Engineering (ESAT) Current TF analysis  p1 –  p2 –  z1 –  z2 – high frequency R eq makes  p1 and  z1 well separated

33. MICAS Department of Electrical Engineering (ESAT) Current TF--Simulation results C tank : 100p I load : 20uA~2m A G m : 4uA/V R C : 1K C aux : 20p F R aux : 100 K 632.5 uA 20 uA 63.25 uA 200 uA TF vs. I Load 2 mA -3dB Peak Freq -3dB

34. MICAS Department of Electrical Engineering (ESAT) Part IV: Future Work Extend the TF measurements into higher frequency, Find a way to linearly inject the AC current, Characterization & quantification of EME from digital circuits, Prediction of EME of digital circuits, Spread spectrum clock generation.

35. MICAS Department of Electrical Engineering (ESAT) Questions Thank you for your attention