1. DSP C5000 Chapter 10 Understanding and Programming the Host Port Interface (EHPI) Copyright © 2003 Texas Instruments. All rights reserved.

2. ESIEE, Slide 2 Understanding and Programming the Host Port Interface (EHPI)

3. Copyright © 2003 Texas Instruments. All rights reserved. Understanding and Programming the Host Port Interface (EHPI)

4. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 4 C55x EHPI Objectives   Describe operation of EHPI   Understand the basic setup required to use the EHPI to perform a task   Describe additional capabilities 20

5. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 5 5510 CPU/Peripheral Architecture Periph Bus Controller Serial Ports Timers GPIO ExternalMemory SARAM(128KW) DARAM(32KW) PDROM(16KW) DMACPU EMIF EHPI  Periph Controller connects periph to CPU  Periph protocol allows maximum interface speed EHPI allows minimal Hardware glue logic to connect the C55x to a standard microprocessor

6. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 6 Summary of EHPI Features  The enhanced host port interface (EHPI) provides a 16-bit-wide parallel port through which a host processor (PC, Microcontroller, DSP) can directly access the memory of the DSP.  The host and the DSP can exchange information via memory internal or external to the DSP.  The EHPI uses 23-bit addresses, each can address a 16-bit word in memory.

7. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 7 EHPI Features  ACCESS: 16-bit port access to 5510’s internal/external (First 1M x 16) memory resources  BOOT: Can boot load DSP’s internal memory during reset  SPEED: 56MBytes/sec @ 200MHz (7 cyc/word, EHPI in “highest” mode)  MODES: Multiplexed Addr/Data, Non-multiplexed (A, D separate) Host Internal Memory 160KW External Memory 864KW EHPI 5510 Let’s see how the EHPI operates...

8. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 8 EHPI Modes of Operation  The DMA controller handles all EHPI accesses.  There are two EHPI access configurations: 1) EHPI shares internal memory with the DMA channels. 2) EHPI has exclusive access to the internal memory.  The EHPI cannot directly access the peripherals of the DSP.  Data from or to the peripherals must be transferred to memory before being transferred to or from the host.

9. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 9 EHPI at Reset  At Reset (reset signal low), the EHPI can access only the internal single-access RAM (SARAM).  The EHPI can prolong the DSP reset process so that the host can load code into the SARAM before the CPU fetches the DSP reset vector.

10. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 10 EHPI Modes  EHPI allows two modes for passing data and addresses to adapt to different possible hosts:  Non-multiplexed bus to the host processor is with separate address and data buses.  Multiplexed mode that provides a single bus to transport address and data information.  Each mode requires different configurations of EHPI signals

11. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 11  EHPI has 3 registers that a host processor can use to access the memory of the DSP: 1)HPID, EHPI data register a temporary storage for data to be transferred through the EHPI (Read or write) 2)HPIA, EHPI address register is used in multiplexed mode to store a 16- or 20-bit address for a read or write operation. Not used in non multiplexed mode where address is available through HA[19:0] 3)HPIC, EHPI control register, is used for transfer control modes  The Host uses HCNTL1 and/or HCNTL0 signal to indicate which EHPI register it accesses.  The DSP can never access in read or write to these registers. EHPI Registers

12. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 12 EHPI Control Reset Bit  HPIC register contents defines EHPI mode of operation:  RESET, bit 0 of HPIC, is cleared when the DSP reset signal is asserted at the pin, and remains 0 after the reset signal returns to the high level. The DSP CPU does not start running until the host sets the RESET bit.  Then host can access the C55x to download code to internal SRAM.  When the download is complete, the host can set the RESET bit to start the CPU after the reset signal returns to the high level. The DSP CPU does not start running until the host sets the RESET bit.

13. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 13 EHPI Control Host to DSP Interrupt Request  The host can send a maskable interrupt request to the DSP CPU by writing a 1 to DSPINT.  If DSPINT bit is 1, the DSP sets the corresponding flag bit (DSPINT) in IFR (see Chap 6).  If the DSPINT is enabled, the CPU will validate the interrupt request and clear the CPU’s DSPINT otherwise, the CPU will ignore it.

14. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 14 Interrupts Between Host and DSP Interrupt Request from the DSP to the Host  The DSP can send an interrupt request to the host by clearing and then setting the HINT bit in status register ST3_55 of the CPU. This will change the HINT output.  No acknowledgment path from the host to the HINT bit.  A space in memory can be shared by the host and the DSP to create an acknowledgment path to the interrupt.  During a DSP reset, the CPU sets the HINT bit and HINT_ goes high (inactive). DSP HCNTL0 HCNTL1 Interrupt Request from the Host to the DSP Non-multiplexed mode, HCNTL0 =0 multiplexed mode, HCNTL1 and HCNTL0=0 Write a 1 to bit DSPINT of HPIC. HINT

15. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 15 EHPI Control Extended Address Enable bit  XADD, bit 5 of HPIC, is used in multiplexed mode only and determines wether values written to HPIA go to HPIA(15-0) or to HPIA(19-16)  In the multiplexed mode of the EHPI, the EHPI address register (HPIA) is loaded via the 16-bit data bus, HD[15:0]. When a 20-bit address is used, HPIA must be loaded with two transfers across HD[15:0] using XADD control.

16. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 16 EHPI Signals Non-multiplexed Mode HD: Data Bus HA: Adress Bus HB: Bit Enable HCS: Chip Select HR/W: Host Read/Write HDS1: Data Strobe HDS2: Data Strobe HRDY: EHPI Ready HCNTL0: EHPI Access HMODE= 1 Non MUX EHPIENA= 1 Enable EHPI HINT: DSP to host Interrupt

17. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 17EHPI EHPI Operation (Non-multiplexed) Host ADCtrl DMA HPIC Control HPID Data 16 HPIAAddr20 DMA Bus HA[19:0] HD[15:0] Control 5510HMODE - multiplexed - non-multi EHPIENA HCNTL0 (accessing HPID or HPIC?)  Hardware Setup - Use HMODE to select multiplexed vs. non-multiplexed address/data - Tie EHPIENA high to use EHPI  Operation - Host presents HA, HD and control ( HCNTL0 picks HPID/HPIC access) - EHPI sets up DMA to perform access, DMA reads/writes, next access What else can the EHPI do? Internal Memory 160KW External Memory 864KW

18. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 18 EHPI Multiplexed mode Multiplexed mode Use HD[15:0] only, shared addr/data bus Data access: write HPIAddress then HPIData, auto- increment available.

19. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 19 Other EHPI Issues HPIC 510 RESETDSPINTXADD  EHPI Boot Load during Reset - Set EHPIENA = 1 - Write HPIC RESET = 1 when done  Interrupts - DSP to Host ( HINT in ST3) - Host to DSP ( DSPINT in HPIC)  Misc Issues - Byte access: use HBE[1:0] - If >64K access required, set XADD to enable HA[19:16] - Fast access? Set EHPI = highest priority in DMA. - EHPI cannot write to peripheral registers (no access to I/O space) CPU RS HPI RS Boot Fetch RS vector HPIC RESET = 1

20. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 20 C54x EHPI

21. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 21 C54x EHPI Objectives   Describe operation of EHPI   Understand the basic setup required to use the EHPI to perform a task   Describe additional capabilities 20

22. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 22 Enhanced Host Port Interface (EHPI)   ACCESS: 8/16-bit port access to 54’s on-chip memory resources   BOOT: Can boot load DSP’s internal memory   SPEED: 33MBytes/sec @ 100MHz (6 cycles/word, max)   MODES: Multiplexed Address/Data, Non-multiplexed (A, D separate) Host Internal Memory EHPI Let’s see how the EHPI operates...

23. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 23 EHPI Operation (Non-multiplexed) EHPI Host A D Ctrl DMA HPIC Control HPID Data y HPIAAddrx DMA Bus HA[x:0] HD[y:0] Control HMODE - multiplexed - non-multi HPIENA   Hardware Setup - Use HMODE to select multiplexed vs. non-multiplexed address/data - Tie HPIENA high to use EHPI   Operation - Host presents HA, HD and control ( HCNTL0 picks HPID/HPIC access) - EHPI sets up DMA to perform access, DMA reads/writes, next access What else can the EHPI do? Internal Memory

24. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 24 Other EHPI Issues   EHPI Bootload during Reset (some devices) - hold device in reset, transfer data, release reset   Interrupts - DSP to Host - Host to DSP   Multiplexed Address/Data lines (Intel access) - Uses HD[15/7:0] only, shared address/data bus   EHPI always has priority to DMA bus   Full Memory Access - Host has full access to internal memory

25. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 25 Chip Support Library   CSL exists to simplify the programming of on-chip peripherals.   The library is primarily written in C and organized into discrete modules with individual APIs. These modules are: CSLTop level module DATDevice independent data copy/fill CHIPDevice specific module DMADirect memory access EBUSExternal memory bus interface GPIOGeneral purpose I/O HPIHost port interface IRQInterrupt controller MCBSPMultichannel buffered serial port PWRPower down STDINCStandard include module TIMERTimer module Refer to SPRU480 for complete information   CSL is configured via the CCS 2.0 BIOS configuration tool