1. Requirements for the PS/PSB TFB board 1 Alfred Blas Working group meeting - 07 December 2011 1.Sampling frequency 2.Required Delayed Clocks

2. 1. Sampling frequency PSB TFB requirements (the most demanding) 2 Alfred Blas 50 MeV to 1.4 GeV PSB with Linac2 Frev  [ 0.6 MHz, 1.73 MHz ] (factor 2.88) 160 MeV to 2 GeV PSB with Linac4 Frev  [ 1 MHz, 1.81 MHz ] (factor 1.81) Sampling rate for having a 20 MHz system analogue bandwidth > 60 Ms/s Present ADC (AD6645) clock frequency range: [ 30 MHz, 105 MHz] DAC (AD9754) clock frequency range: [ DC, 125 MHz] Present limitation for the sampling frequency : 60 MHz < f S < 105 MHz The ratio 105/60 = 1.75 < 1.81 is marginally compatible with a use in the PSB during the Linac4 era ! < 2.88 means it is not compatible with Linac 2! Working group meeting - 07 December 2011

3. 1.Sampling frequency Proposed improvements 3 Alfred Blas Use an ADC with a maximum sampling frequency > 125 MHz. This would allow to use the Clock used for the RF (max = 125 MHz) Allow for a clock harmonic change (no hardware implication): The clock frequency will be measured in the FPGA to detect the harmonic change When the change is detected, the loop will remain inactive during the purging of the loop Registers will be loaded with the sequence of different harmonics used within the cycle Working group meeting - 07 December 2011

4. 2.Required Delayed Clocks 4 Alfred Blas DP RAM RF Clk RF Clk + calculated Δt Data in Write Address Data out Read Address Counter Calculated pipeline delay Ck 2 different clock domains ! Write Read 2 setups of this kind: One to track the flight time change between two PUs One ------------------------------------------------------------------------------------------PU and Kicker Fine Dly Working group meeting - 07 December 2011

5. 2.Required Delayed Clocks 5 Alfred Blas When the required fine delay Δ T < t pd + th, the read address needs to be latched with CK (t pd = CK to data out propagation delay, t h = flip-flop hold time) When t pd + th < Δ T < T CK the read address needs to be latched with /CK (inverted CK) Working group meeting - 07 December 2011

6. 2.Required Delayed Clocks 6 Alfred Blas When Δ T is equal to 8.8 ns when programmed to zero as in the present case, the delayed clock handling becomes complicated. First the offset value needs to be known and well displayed somewhere Second, the designer needs to handle a special case when the clock period passes through 8.8ns at113 MHz Working group meeting - 07 December 2011

7. 7 Alfred Blas 2.Required delayed clocks ADC Data synchronization ADC conversion time: 1.4  t C  7ns FPGA flip-flop hold time = 1ns? Longer path in the FPGA from pin to F-F compared pin to clock path :3ns? Working group meeting - 07 December 2011

8. 8 Alfred Blas RF Clock ADC #2 ADC #1 Δ T offset + Δ T var 2 Δ t offset Δ T ADC DPRAM DFF Beam ProcessDPRAM Δ T offset + Δ T var 1 DAC 5 clock delays in total maybe 6 ? ? Working group meeting - 07 December 2011

9. 9 Alfred Blas RF Clock ADC #2 ADC #1 Δ T offset + Δ T var 2 Δ T ADC DPRAM DFF Beam ProcessDPRAM Δ T offset + Δ T var 1 DAC Simplified version 4 clock delays in total maybe 5 ? ΔT DAC ? Working group meeting - 07 December 2011

10. 10 Alfred Blas RF Clock ADC #2 ADC #1 DPRAM DFF Beam ProcessDPRAM Δ T offset + Δ T var 2 DAC Present state Working group meeting - 07 December 2011 Cannot create a fine delay Δ T offset + Δ T var 1 Possible acq. problem

11. 3.Effect of a delay change 11 Alfred Blas DP RAM Ck Ck + calculated Δt Data in Write Address Data out Read Address Counter Calculated pipeline delay Ck Write Read During an accelerating cycle the automatic delay will decrease in the following way: Smooth decrease of the fine delay Δt down to zero -> then decrease of one pipeline stage together with an abrupt increase of the fine delay Δ t of about one clock period. Opposite behavior in a decelerating cycle. Working group meeting - 07 December 2011

12. 3.Effect of delay change 12 Alfred Blas This delay transition (decrease of one pipeline stage) should be smooth with no glitch. The memorized clock signal in the fine delay total length has no side effect (assuming a smooth functioning of the file delay chip). Working group meeting - 07 December 2011

13. 4.Summary 13 Alfred Blas 1.The ADCs should be upgraded for a 125 MHz version (why not 16 bits) 2.The clock distribution should be implemented as described in slide 10. 3.There is no need for the sophisticated (and unfortunately not operational in all circumstances) delay switching circuit. Working group meeting - 07 December 2011