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Dirk Stroobandt Ghent University Electronics and Information Systems Department A Priori System-Level Interconnect Prediction Rent’s Rule and Wire Length.

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Presentation on theme: "Dirk Stroobandt Ghent University Electronics and Information Systems Department A Priori System-Level Interconnect Prediction Rent’s Rule and Wire Length."— Presentation transcript:

1 Dirk Stroobandt Ghent University Electronics and Information Systems Department A Priori System-Level Interconnect Prediction Rent’s Rule and Wire Length Distribution Models Tutorial at SLIP 2001 March 31, 2001

2 Dirk Stroobandt, SLIP 2001 2 Why a priori interconnect prediction? Basic models Rent’s rule A priori wire length prediction Recent advances Outline

3 March 31, 2001Dirk Stroobandt, SLIP 2001 3 Why a priori interconnect prediction? Basic models Rent’s rule A priori wire length prediction Recent advances Outline

4 March 31, 2001Dirk Stroobandt, SLIP 2001 4 Interconnect: importance of wires increases (they do not scale as components). A priori: For future designs, very little is known. The sooner information is available, the better. A Priori Interconnect Prediction = estimating interconnect properties and their consequences before any layout step is performed. Extrapolation to future systems: Roadmaps. To improve CAD tools for design layout generation. To evaluate new computer architectures. Why A Priori Interconnect Prediction?

5 March 31, 2001Dirk Stroobandt, SLIP 2001 5 Extrapolation to future systems: Roadmaps. GTX* et al. Why A Priori Interconnect Prediction? * A. Caldwell et al. “GTX: The MARCO GSRC Technology Extrapolation System.” IEEE/ACM DAC, pp. 693-698, 2000 (http://vlsicad.cs.ucla.edu/GSRC/GTX/).

6 March 31, 2001Dirk Stroobandt, SLIP 2001 6 To improve CAD tools for design layout generation. Why A Priori Interconnect Prediction? More efficient layout generation requires good wire length estimates. layer assignment in routing effects of vias, blockages congestion,... A priori estimates are rough but already provide a better solution through fewer design cycle iterations.

7 March 31, 2001Dirk Stroobandt, SLIP 2001 7 Why A Priori Interconnect Prediction? To evaluate new computer architectures OIIC Project (http://www.elis.rug.ac.be/~jvc/oiic/sysdemo.htm)

8 March 31, 2001Dirk Stroobandt, SLIP 2001 8 Goal: Predict Interconnect Requirements vs. Resource Availability

9 March 31, 2001Dirk Stroobandt, SLIP 2001 9 Circuit designFabricationPhysical design Setting of SLIP Research Domain in the Design Process

10 March 31, 2001Dirk Stroobandt, SLIP 2001 10 Components of the Physical Design Step Layout Layout generation CircuitArchitecture

11 March 31, 2001Dirk Stroobandt, SLIP 2001 11 Net Terminal / pin The Three Basic Models Circuit model Placement and routing model Model for the architecture Pad Channel Manhattan grid using Manhattan metric Cell Logic block

12 March 31, 2001Dirk Stroobandt, SLIP 2001 12 Why a priori interconnect prediction? Basic models Rent’s rule A priori wire length prediction Recent advances Outline

13 March 31, 2001Dirk Stroobandt, SLIP 2001 13 T = t B p Rent’s Rule (simple) 0  p*  1 (complex) Normal values: 0.5  p*  0.75 Measure for the complexity of the interconnection topology Intrinsic Rent exponent p* p = Rent exponent Rent’s rule was first described by Landman and Russo* in 1971. For average number of terminals and blocks per module in a partitioned design: t  average # term./block * B. S. Landman and R. L. Russo. “On a pin versus block relationship for partitions of logic graphs.” IEEE Trans. on Comput., C-20, pp. 1469-1479, 1971.

14 March 31, 2001Dirk Stroobandt, SLIP 2001 14 Rent’s Rule (cont.) Rent’s rule is a result of the self-similarity within circuits Assumption: the complexity of the interconnection topology is equal at all levels.

15 March 31, 2001Dirk Stroobandt, SLIP 2001 15 BB TT If  B cells are added, what is the increase  T? In the absence of any other information we guess Overestimate: many of  T terminals connect to T terminals and so do not contribute to the total. We introduce* a factor p (p <1) which indicates how self-connected the netlist is + placement optimization Or, if  B &  T are small compared to B and T Statistically homogenous system T B Rent’s Rule (other definition) (Dense) region: B cells, T terminals * P. Christie and D. Stroobandt. “The Interpretation and Application of Rent’s Rule.” IEEE Trans. on VLSI Systems, Special Issue on SLIP, vol. 8 (no. 6), pp. 639-648, Dec. 2000.

16 March 31, 2001Dirk Stroobandt, SLIP 2001 16 Rent’s Rule (summary) average Rent’s rule Rent’s rule is experimentally validated for a lot of benchmarks. T = t B p Distinguish between: p*: intrinsic Rent exponent p: placement Rent exponent p’: partitioning Rent exponent Deviation for high B and T: Rent’s region II* Also: deviation for low B and T: Rent region III** ** D. Stroobandt. “On an efficient method for estimating the interconnection complexity of designs and on the existence of region III in Rent’s rule.” Proc. GLSVLSI, pp. 330-331, 1999. * B. S. Landman and R. L. Russo. “On a pin versus block relationship for partitions of logic graphs.” IEEE Trans. on Comput., C-20, pp. 1469-1479, 1971.

17 March 31, 2001Dirk Stroobandt, SLIP 2001 17 Why a priori interconnect prediction? Basic models Rent’s rule A priori wire length prediction Recent advances Outline

18 March 31, 2001Dirk Stroobandt, SLIP 2001 18 1. Partition the circuit into 4 modules of equal size such that Rent’s rule applies (minimal number of pins). 2. Partition the Manhattan grid in 4 subgrids of equal size in a symmetrical way. Donath’s* Hierarchical Placement Model * W. E. Donath. Placement and Average Interconnection Lengths of Computer Logic. IEEE Trans. on Circuits & Syst., vol. CAS-26, pp. 272-277, 1979.

19 March 31, 2001Dirk Stroobandt, SLIP 2001 19 3. Each subcircuit (module) is mapped to a subgrid. 4. Repeat recursively until all logic blocks are assigned to exactly one grid cell in the Manhattan grid. Donath’s Hierarchical Placement Model mapping

20 March 31, 2001Dirk Stroobandt, SLIP 2001 20 Donath’s Length Estimation Model At each level: Rent’s rule gives number of connections number of terminals per module directly from Rent’s rule (partitioning based Rent exponent p’); number of nets cut at level k (N k ) equals where  depends on the total number of nets in the circuit and is bounded by 0.5 and 1.

21 March 31, 2001Dirk Stroobandt, SLIP 2001 21 Donath’s Length Estimation Model Length of the connections at level k ? Donath assumes: all connection source and destination cells are uniformly distributed over the grid. Adjacent ( A -) combination Diagonal ( D -) combination

22 March 31, 2001Dirk Stroobandt, SLIP 2001 22 Results Donath Scaling of the average length L as a function of the number of logic blocks G : L G 0 5 10 15 20 25 30 11010010 3 10 6 10 5 10 4 10 7 p = 0.7 p = 0.5 p = 0.3 Similar to measurements on placed designs.

23 March 31, 2001Dirk Stroobandt, SLIP 2001 23 Results Donath Theoretical average wire length too high by factor of 2 10000 L G 1 2 3 4 6 5 7 101001000 8 experiment theory 0

24 March 31, 2001Dirk Stroobandt, SLIP 2001 24 Occupation probability* favours short interconnections (for placement optimization) (darker) Keep wire length scaling by hierarchical placement. Improve on uniform probability for all connections at one level (not a good model for placement optimization). Improving on the Placement Optimization Model * D. Stroobandt and J. Van Campenhout. Accurate Interconnection Length Estimations for Pre- dictions Early in the Design Cycle. VLSI Design, Spec. Iss. on PD in DSM, 10 (1): 1-20, 1999.

25 March 31, 2001Dirk Stroobandt, SLIP 2001 25 Including Placement Optimization Wirelength distributions contain two parts: site density function and probability distribution all possibilities requires enumeration (use generating polynomials*) probability of occurrence shorter wires more probable * D. Stroobandt and H. Van Marck. “Efficient Representation of Interconnection Length Distributions Using Generating Polynomials.” Workshop SLIP 2000, pp. 99-105, 2000.

26 March 31, 2001Dirk Stroobandt, SLIP 2001 26 Occupation Probability Function From this we can deduct that Local distributions at each level have similar shapes (self-similarity)  peak values scale. Integral of local distributions equals number of connections. 1 10 100 1000 110100 Wire length Theory Experiment L p,1 P1P1 L 1,l L p,2 P2P2 L 2,l L p,0 P0P0 L 0,l DlDl 246810121416 Length l Number of connections For short lengths: Global distribution follows peaks.

27 March 31, 2001Dirk Stroobandt, SLIP 2001 27 Occupation Probability Function Same result found by using a terminal conservation technique* * J. A. Davis et al. A Stochastic Wire-length Distribution for Gigascale Integration (GSI) - PART I: Derivation and Validation. IEEE Trans. on Electron Dev., 45 (3), pp. 580 - 589, 1998. C BA C BA C BA C BA C BA =+-- TACTAC TABTAB T BC TBTB T ABC = +-- Assumption: net cannot connect A,B, and C B B BB BB B ABB BB B C C C C C C C C C C C C

28 March 31, 2001Dirk Stroobandt, SLIP 2001 28 Occupation Probability Function For cells placed in infinite 2D plane B B BB BB B ABB BB B C C C C C C C C C C C C

29 March 31, 2001Dirk Stroobandt, SLIP 2001 29 Occupation Probability: Results 8 Occupation prob. 10000 L G 1 2 3 4 6 5 7 101001000 0 Donath Experiment Use probability on each hierarchical level (local distributions).

30 March 31, 2001Dirk Stroobandt, SLIP 2001 30 Occupation Probability: Results Effect of the occupation probability: boosting the local wire length distributions (per level) for short wire lengths Occupation prob. 100 Wire length Percent of wires 10 1 0,1 0,01 10 -3 10 -4 100001101001000 Per level Total Global trend Donath 1 Wire length 101001000 Per level Total Global trend 10000

31 March 31, 2001Dirk Stroobandt, SLIP 2001 31 Effect of the occupation probability on the total distribution: more short wires = less long wires  Average wire length is shorter Occupation Probability: Results 100 10 1 10 -1 10 -2 10 -3 10 -4 10 -5 110100100010000 Wire length Percent wires Occupation prob. Donath

32 March 31, 2001Dirk Stroobandt, SLIP 2001 32 Occupation Probability: Results 10 20 30 40 50 60 110 Wire length Percent wires Occupation prob. Donath 2 345678 9 Global trend -23% -8% +10% +6%

33 March 31, 2001Dirk Stroobandt, SLIP 2001 33 Occupation Probability: Results 0,1 1 10 100 1000 1100 Wire length Number of wires Occupation prob. Donath Measurement 10

34 March 31, 2001Dirk Stroobandt, SLIP 2001 34 Why a priori interconnect prediction? Basic models Rent’s rule A priori wire length prediction Recent advances Outline

35 March 31, 2001Dirk Stroobandt, SLIP 2001 35 Length of Multi-terminal Nets Difference between delay-related and routing-related applications*: - Source-sink pairs Assume A is source A-B at level k A-C and A-D at level k+1 Count as three connections - Entire Steiner tree lengths Segments A-B, C-D and E-F A-B and C-D at level k E-F at level k+1 Add lengths to one net length A B C D Level k +1 Level k F E Net terminal Steiner point * D. Stroobandt. “Multi-terminal Nets Do Change Conventional Wire Length Distribution Models.” Workshop SLIP 2001.

36 March 31, 2001Dirk Stroobandt, SLIP 2001 36 Extension to Three-dimensional Grids* * D. Stroobandt and J. Van Campenhout. “Estimating Interconnection Lengths in Three- dimensional Computer Systems.” IEICE Trans. Inf. & Syst., Spec. Iss. On Synthesis and Verification of Hardware Design, vol. E80-D (no. 10), pp. 1024-1031, 1997. * A. Rahman, A. Fan and R. Reif. “System-level Performance Evaluation of 3-dimensional Integrated Circuits.” IEEE Trans. on VLSI Systems, Spec. Iss. on SLIP, pp. 671-678, 2000.

37 March 31, 2001Dirk Stroobandt, SLIP 2001 37 Anisotropic Systems* * H. Van Marck and J. Van Campenhout. Modeling and Evaluating Optoelectronic Architectures. Optoelectronics II, vol. 2153 of SPIE Proc. Series, pp. 307-314, 1994.

38 March 31, 2001Dirk Stroobandt, SLIP 2001 38 Anisotropic Systems Not all dimensions are equal (e.g., optical links in 3rd D) Possibly larger latency of the optical link (compared to intra- chip connection); Influence of the spacing of the optical links across the area (detours may have to be made); Limitation of number of optical layers Introducing an optical cost

39 March 31, 2001Dirk Stroobandt, SLIP 2001 39 External Nets Importance of good wire length estimates for external nets* during the placement process: For highly pin-limited designs: placement will be in a ring-shaped fashion (along the border of the chip). * D. Stroobandt, H. Van Marck and J. Van Campenhout. Estimating Logic Cell to I/O Pad Lengths in Computer Systems. Proc. SASIMI’97, pp. 192-198, 1997.

40 March 31, 2001Dirk Stroobandt, SLIP 2001 40 Wire Lengths at System Level At system level: many long wires (peak in distribution). How to model these? Estimation* based on Rent’s rule with the floorplanning blocks as logic blocks. * P. Zarkesh-Ha, J. A. Davis and J. D. Meindl. Prediction of Net length distribution for Global Interconnects in a Heterogeneous System-on-a-chip. IEEE Trans. on VLSI Systems, Spec. Iss. on SLIP, pp. 649-659, 2000.

41 March 31, 2001Dirk Stroobandt, SLIP 2001 41 Conclusion Wire length distribution estimations have evolved a lot in the last few years and have gained accuracy but the work is not finished! Suggested reading (brand new book): D. Stroobandt. A Priori Wire Length Estimates for Digital Design. Kluwer Academic Publishers, 2001. 324 pages, ISBN no. 0 7923 7360 x.

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