1. 1 Test Setups for the FE-I4 Integrated Circuit Stewart Koppell 8/1/2010

2. 2 Test Hardware – USBPix System

3. 3 Hardware – USBPix System Emulator (bottom) The USBPix System has 3 main components: 1.Main Board: Contains SRAM, FPGA, microcontroller. Responsible for translating commands into signals to be sent to IC and interpreting/parsing the output. Communicates with a computer via USB cable 2. Single Chip Adapter Card: Extension of the Main board that can be exchanged to allow the system to interface with multiple FE-I4s. The Adapter Card also translates the outgoing signal into LVDS. 2 1

4. 4 Hardware – USBPix System 3. Add-on Card: Mount for the emulator/FE-I4. It connects to the Adapter Card via type-0 Cable An alternative setup replaces the Type-0 Cable and Add-on Card with: Pin card: Connects to Adapter Card with a flat ribbon cable. Allows data input/output and clock signals to be accessed from pins. Carrier Board: Connects to the Pin card by jumper wires. Mount for emulator/FE-I4. 3 3 Emulator (bottom)

5. 5 Emulator While the FE-I4 is being fabricated, debugging of the testing hardware and software will be done using a stand-in emulator. The central component of the emulator is an FPGA, which was configured using VHDL. emulator versions: Version 0: sends out a constant stream of words (i.e. 0x abc123, 0x efg789). In the USBPix system they are parsed and stored in the SRAM where they can be retrieved by the testing software. Version 1: implements a few 16 bit configuration registers

6. 6 Commands Level 1 trigger: 11101 Calibration pulse: 10110 0100 Write Register: 10110 1000 0010 1000 00010 1111111111111111 Write Front End: 10110 1000 0100 0000 000000 1111111111111111 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111 Slow Command Header WrRegChip IDRegister Address Register Data

7. 7 Test Software Arbitrary Bit Stream Generator (ABSG) The ABSG allows a user to generate bit streams representing standard commands by pressing buttons. Once a bit stream is generated, it can be edited by hand before being sent out through the USBPix hardware.

8. 8 Software: Arbitrary Bit Stream Generator (ABSG)

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10. 10 Software: Arbitrary Bit Stream Generator (ABSG)

11. 11 Software: Arbitrary Bit Stream Generator (ABSG)

12. 12 Software: Arbitrary Bit Stream Generator (ABSG)

13. 13 Test Software: Pixel Manager The Pixel Manager provides a visual representation of the FE-I4 which can be used to activate and deactivate arbitrary regions of pixels. One double column at a time is shown (center left), with buttons which control the activation state of groups of 21 pixels. The adjacent View buttons display the pixels in the corresponding rows (center left) which can be individually activated or deactivated.

14. 14 Test Software: Pixel Manager

15. 15 Test Software: Pixel Manager

16. 16 Test Software: Pixel Manager

17. 17 Test Software: Pixel Manager FE pixel = 2 x 10 pixels on screen. Dark Grey=off Light Grey=on Green=hit (darker=stronger)

18. 18 Parser #config PrmpVbp_r 1 5 0xFF00 50 Vthin 2 5 0x00FF 64 DisVbn_CPPM3 6 0xFF00 64 PrmpVbp4 6 0x00FF 32 TdacVbp 5 7 0xFF00 0 DisVbn 6 7 0x00FF 128 Amp2Vbn7 8 0xFF00 69 Amp2VbpFol8 8 0x00FF 26 PrmpVbp_T9 9 0xFF00 66 Amp2Vbp10 9 0x00FF 64 FdacVbn11 10 0xFF00 66 Amp2Vbpff12 10 0x00FF 175 PrmpVbnFol13 11 0xFF00 64 PrmpVbp_L14 11 0x00FF 66 PrmpVbpf15 12 0xFF00 16 PrmpVbnLcc16 12 0x00FF 0 Spare117 13 0x0001 0 PixelStrobes18 13 0x3FFE 16380 S019 13 0x4000 0 S120 13 0x8000 1 LvdsIref21 14 0xFF00 0 BonnDac22 14 0x00FF 0 PllIbias23 15 0xFF00 0 LvdsDrvVos24 15 0x00FF 0 TempSensBias25 16 0xFF00 0 PllIcp26 16 0x00FF 0 DAC8SPARE127 17 0xFF00 0 PlsrIdacRamp28 17 0xFF00 0 #taskdefine task1 comm,wrRegister,vthin,24 comm,rdRegister,tdacvbp comm,rdRegister,vthin endtask task2 comm,rdRegister,tdacvbp comm,wrRegister,tdacvbp,100 comm,rdRegister,tdacvbp endtask #command comm,wrRegister,vthin,17 comm,rdRegister,tdacvbp task,task1 comm,rdRegister,disvbn loop,5,task,task2 loop,5,comm,wrRegister,vthin,10 3 types of files: ConfigurationTask Command

19. 19 Parser

20. 20 Test Hardware – SLAC system The other used hardware setup. It uses an Ethernet DHCP server connection rather than a USB cable to connect to the computer. The RCE and Controller (comparable in function to the USBPix main board) are housed in a two-slot ATCA electronics crate. The HSIO (comperable in function to the Single Chip Adapter Card) is connected to the ATCA crate with optical fiber and communicates directly with the emulator/FE-I4.

21. 21 Conclusions The ABSG and Pixel manager extend the functionality of the USBPix software by allowing more convenient ways of testing and configuring the FE-I4 The ABSG allows: testing of chip response to single Event Upsets (SEU) by manually flipping bits before sending a command testing of chip response to various ways of ordering and timing of commands The Pixel Manager allows: arbitrary regions of pixels on the chip to be activated/deactivated for testing generation of a colored map of the chip representing the activation state of pixels and the locations/strengths of hits