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Test structures for the evaluation of TowerJazz 180 nm CMOS Imaging Sensor technology  ALICE ITS microelectronics team - CERN.

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Presentation on theme: "Test structures for the evaluation of TowerJazz 180 nm CMOS Imaging Sensor technology  ALICE ITS microelectronics team - CERN."— Presentation transcript:

1 Test structures for the evaluation of TowerJazz 180 nm CMOS Imaging Sensor technology  ALICE ITS microelectronics team - CERN

2 TID_TJ180 layout 3.7 mm 2.2 mm CMOS test structures with Deep p-well Breakdown diodes ALICE ITS microelectronics team - CERN Tower Jazz 0.18 um CMOS Imaging Sensor 2

3 CMOS test structures 2.0 mm 1.2 mm 16 x 8 pad matrix = 128 pads Pad opening size: 76 μm x 76 μm Each block has an individual power supply and it can be tested individually. Block A Block B Block C Block D 167 μm, 100 μm, 167 μm, 125 μm, 167 μm, 100 μm, 167 μm 125 μm ALICE ITS microelectronics team - CERN 125 μm horizontal pitch 100 μm, 125 μm, 167 μm vertical pitch 3

4 MOS devices * Low Vt transistors cannot be used in a design with High Vt transistors 78 MOS with different sizes and t ox and V th options Layout examples NMOS in a Triple Well (Deep N-Well) for P-well isolation and noise immunity NMOS Enclosed Layout NMOS PMOS  m ALICE ITS microelectronics team - CERN4

5 MOS test structures arrays ALICE ITS microelectronics team - CERN Extraction of effective L. Radiation effect dependency on the gate length. L array: W = 10  m, different L Extraction of effective W. Study of the Radiation Induced Narrow Channel Effect (RINCE). W array: L = 0.18  m, different W Study of the transistor behaviour as a function of the size. W/L = 10 Noise measurement. (NMOS in triple well) W/L = 600 Array Purpose 5

6 Other devices 6ALICE ITS microelectronics team - CERN

7 Breakdown diodes 7ALICE ITS microelectronics team - CERN Cross section nwell diode nwell with deep pwell in the between Measurements: Breakdown voltage and depletion layer capacitance depleted volume depleted volume p + : -30 V; n + : 0 V NW width: 1 µm or 2 µm NW with DPW width: up to 3.40 µm

8 Single Event Effects evaluation test chip 8ALICE ITS microelectronics team - CERN -SP RAM: 16 macro blocks, 1024 x 16 bit -DP RAM: 8 macro blocks, 2048 x 16 bit -16 bit 32 K stages D-Flip-Flop shift register ALICE_ITS_TJ180_T1

9 SEU_TJ180 layout 9ALICE ITS microelectronics team - CERN 4872 µm 4454 µm SP_RAM DP_RAM Shift Register

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